0
\$\begingroup\$

Could someone tell me what a typical rise time would be for a 2 MHz SPI clock signal driven by an Arduino Micro (ATmega32U4), off the SCK pin? An actual measurement would be preferable, but I do not have the means to do that myself.

Am I right in assuming this would give me a lower limit for the rise times in a circuit driven by the Arduino SCK signal?

I could not find any useful information about the actual rise time on the web: not in the Arduino docs, nor on the Arduino forums, nor here on EE. The ATmega32U4 spec sheet only specifies an upper limit for SPI rise time at 1600 ns, as far as I can see.

Based on the clock frequency of 2 MHz I could assume a rise time of 1% of the clock period, i.e. 5 ns, but that would not be much better than a random guess.

\$\endgroup\$
  • 4
    \$\begingroup\$ It depends on the load R, L and C attached. \$\endgroup\$ – Colin May 30 '19 at 11:45
  • \$\begingroup\$ @Colin: Thanks. I'm interested in the rise time of the signal if measured directly at the Arduino SCK pin, using a proper high performance scope and probes. Assuming that would be the lowest possible rise time... Or could a different load also cause a decrease in rise time (i.e. a faster edge)? \$\endgroup\$ – djvg May 30 '19 at 11:52
  • 2
    \$\begingroup\$ @djvg generally, you'd want impedance matching for the cleanest edge; your high-impedance measurement might see a faster edge, but that will overshoot, then undershoot, then overshoot and so on until it settles. What's the purpose of your measurement? What do you want to do with the resulting number? \$\endgroup\$ – Marcus Müller May 30 '19 at 12:39
  • \$\begingroup\$ @MarcusMüller: Basically I want to know if I need to worry much about high-speed design issues. A 2 MHz clock sounds (relatively) low speed to me, but I believe it is all about the rise time, rather than the clock frequency. I am just trying to establish a realistic lower limit for the rise times I might encounter in my design, as a worst case. I'm hoping I won't have to bother with many high speed issues. \$\endgroup\$ – djvg May 30 '19 at 13:19
  • 1
    \$\begingroup\$ You're looking at it the wrong way. What matters is what gets to the receiving end, and what radiates. What the chip does in isolation is entirely irrelevant; it's not even enough to develop a model of how it would behave in use. \$\endgroup\$ – Chris Stratton May 30 '19 at 14:57
1
\$\begingroup\$

Some MPU output drivers have controlled-slew-rates that are set by configuration bits.

ICs can easily produce 100 picosecond edges. But 100pS and 100 picoFarad loads will produce, given 5 volt edges, using Iout = C * dV/dT, I = 100pF * 5v/100pS = 5 ampere currents. Thus controlled slew is required to avoid collapsing the MCU rails and upsetting the internal state (flipflops getting trashed).

Thus 1/100th of that, or 50 milliAmps, will be a typical maximum output current. That will produce 10 nanosecond edges into 100pF loads, or 1 nanosecond edge into 10pF loads. Controlled-slew output drivers can reduce this Cload-dependent behavior to about 3:1 behavior over process and temperature and (moderate) CLoad values. Examine the USB waveform specifications, for how controlled a slewrate is possible; note the USB has maximum length limits and maximum # of nodes.

On an SPI, select the slew-rate if possible, and use moderate capacitive loads. And then consider inserting 100 ohm resistors at the signal sources, for "source terminated" behavior.

The minimum capacitance on a line, composed of the reversed-bias drain-bulk diodes and the ESD structures of the output, and similar ESD structures and FET gate-bulk (and Miller effect of gate-drain overlap capacitance), will be approximately 10pF.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ Thanks for the great answer. Unfortunately I could not find anything about slew-rate selection for the ATmega32U4, but I'll have a closer look at your other suggestions. \$\endgroup\$ – djvg May 30 '19 at 14:48
  • 1
    \$\begingroup\$ If you do want to establish a slew-rate, place a 100 ohm in series, right at the output, immediately followed by 100pF capacitor, or 470pF, or 1,000pF. The 100 ohm limits the current into the capacitor, and the cap defines a clean 1-pole rise and fall time. \$\endgroup\$ – analogsystemsrf May 30 '19 at 16:00
0
\$\begingroup\$

If someone measured the rise time on their ATmega chip that value may not be the same for your ATmega chip. If you really want to know a value that you can use for design purposes then you must take the maximum value specified in the datasheet.

Assuming a rise time of 1% of the clock period seems arbitrary and very optimistic. There is a disadvantage in having edges that are too fast...fast edges require high current and introduce noise into the power supply voltages. The SPI interface doesn't need to run at tens of megahertz so there is no benefit in having rise times that are faster than necessary.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ Thanks. Still, any measurement would be better than knowing nothing, in my opinion, if only to get an idea of the order of magnitude. The maximum value in the datasheet is 1600ns, but for 500ns period (2 MHz) that does not make much sense. Actually I am looking for the minimum value, so the fastest edge the atmega can generate, as a worst case approximation. I don't want fast edges, because I don't want to have to bother too much with high-speed design stuff. \$\endgroup\$ – djvg May 30 '19 at 13:24

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.