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I've been looking at the PCB layout for the LT3045, a high PSRR LDO. The datasheet of the LT3045's demo board, the DC2491A, includes a recommended PCB layout. One section of the datasheet mentions that the output capacitor, C2, should be mounted on the PCB using a "split capacitor" technique. I'll attach sections of the datasheet that mention this, as well as an accompanying image from the datasheet. enter image description here enter image description here I don't understand how to achieve the capacitor mounting style for C2 in Autodesk EAGLE.

As a side note, why does this PCB design include the vias in the bottom right part of the board? These don't seem to connect to anything.

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  • \$\begingroup\$ When you shunt via inductance with many, it reduces /n vias, also thermal conductance rises. \$\endgroup\$ May 31 '19 at 4:01
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You'd have to make a custom footprint for the capacitor to get this result. It would look like a three terminal device in the layout. The schematic symbol / library part can express that two physical pins (pads) are connected to the same electrical net (pin) in the symbol. In Eagle you Ctrl+click the schematic footprint pads in the part definition pin-pad mapping dialog. It looks like this:

enter image description here

On the sidenote, I'm guessing those apparently orphaned vias are meant to stitch disparate ground planes together at multiple points to make them look more like a unified ground plane electrically.

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  • \$\begingroup\$ And thermally. I consider each via to be approximately 70 degree Centigrade per watt of thermal resistance, if the ratio of height to periphery is 1:1. Given the 30+ vias, the two GND planes should be just 2 degree Centigrade/watt of thermal gradient, in the region of the vias. These numbers for 1 ounce/squarefoot foil (the standard thickness 1.4 mils) \$\endgroup\$ May 31 '19 at 3:49

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