I am implementing a TRNG on an FPGA. This TRNG is based on jitter created by ring oscillator and I would like to know how to implement the given ring oscillator on FPGA so that jitter is generated.

module rng(start, r_out);
input start /* synthesis keep */;
reg rout /* synthesis keep */;
output r_out;
wire n0 /* synthesis keep */;
wire n1 /* synthesis keep */;
wire n2 /* synthesis keep */;
wire n3 /* synthesis keep */;
wire n4 /* synthesis keep */;
wire n5 /* synthesis keep */;
wire n6 /* synthesis keep */;
and a(n6,r0,start);
mynot x1(n6,n0);
mynot x2(n0,n1);
mynot x3(n1,n2);
mynot x4(n2,n3);
mynot x5(n3,n4);
mynot x6(n4,n5);
mynot x7(n5,r_out);

module mynot(
    input x,
    output wire y

This is my code for ring oscillator.

module rng_tb;
reg start;
wire q;
rng uut(start,q);
#50 start=1;

This is the code for testbench.

The output now is don't care.

  • \$\begingroup\$ Have you tried to implement few of the oscillators and there was no jitter? \$\endgroup\$
    – Eugene Sh.
    May 31, 2019 at 16:00
  • \$\begingroup\$ I have tried it and there is no output on simulation. The output is Z or it is in high impedance state. \$\endgroup\$ May 31, 2019 at 16:02
  • \$\begingroup\$ Well, I would not expect to get any jitter on simulation as it is deterministic. You might want to add your code and the simulation results to the question. \$\endgroup\$
    – Eugene Sh.
    May 31, 2019 at 16:03
  • \$\begingroup\$ I would not expect for this implementation to yield Z but rather "X" - unknown state, as you don't have initial values for the values for your simulation to consider. \$\endgroup\$
    – Eugene Sh.
    May 31, 2019 at 16:22
  • 2
    \$\begingroup\$ Beware that it is very, very difficult to build that type of structure with an FPGA. Even using KEEP-this and KEEP-that, the tool tends to optimize out almost all of your gates. Check the post-implementation result of what really, really has been left of your gates at the end!! And NO, it will not give you TRNG. If it was that easy to make a TRNG, more people would be using it. e.g. your ring oscillators will be influenced by the power noise generated from your system clock and each other. \$\endgroup\$
    – Oldfart
    May 31, 2019 at 16:30

1 Answer 1


This is not a ring oscillator, because r0 is unknown. You probably meant r_out:

and a(n6,r_out,start);

Also see: rout vs r_out.

If you correct your topology, you will run into another problem: a timing (delta) loop, basically a correct ring oscillator without delays will hang your simulator at 0 time. You will have to introduce a delay in your "mynot" macro to allow for exiting the delta steps from time 0.


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