0
\$\begingroup\$

I designed a simple adjustable constant current source that uses high side sensing but I can't seem to figure out where the oscillations on my output are coming from. The circuit is shown in a picture below and is designed to have a maximum current output of 2A. In simulation everything works as intended but when I populated my PCB I get really bad oscillations.

High Side Current Sensing Circuit

The potentiometer on the left is a 10k pot. The P-Channel MOSFET that is doing the switching is an FQP17P06 with a large heat sink and the two opamps are an LM4562MAX being driven with 12V on the positive rail and GND connected to the negative rail.

The output of my real circuit tracks the potentiometer set point roughly but oscillates wildly sometimes +-1.5A. The upper limit is also off. When I turn the potentiometer all the way up as shown in the picture my max current measured with a scope and a power supply is somewhere around 2.8-3A which is a lot higher than my intended 2A and is blowing my 2.5A fuse not shown.

Did I do something wrong by using the FET driving OpAmp in open loop mode or are the OpAmps powered ineffectively so they are behaving erratically near the rails?

Current Source Simulation

EDIT (2019-June-11): I attempted to recreate the oscillations by making the circuit components more realistic in both Falstad and then in LTSpice and both refused to simulate or locked up. Turns out my computer was on the fritz and I had to borrow a different one to get a good simulation.

Adding Cgd to the FET and updating the beta value to 1/Rdson as suggested did cause the output to oscillate. I was then able to get it to stabilize using the recommended answer of slowing down the FET driving opamp with an integrator.

\$\endgroup\$
  • \$\begingroup\$ (1) What's with the opamp that has no feedback? If used as an op-amp it needs negative feedback. If used as a comparator, it needs positive feedback for hystersis since real signals are noisy and rapidly move and below the switcing thresholds when near it. (2) Did you add decoupling capacitors? (3) Show us your oscillating waveforms. \$\endgroup\$ – DKNguyen May 31 at 20:30
  • \$\begingroup\$ I'll try to grab a scope trace soon. Does it need its own feedback or is the feedback loop through the other op-amp enough? The left amp controls the P-FET and that directly affects the current through the sense resistor doesn't that provide indirect feedback to the positive terminal through the differential amplifier? \$\endgroup\$ – Wired365 May 31 at 20:30
  • \$\begingroup\$ Yes I have 100uF decoupling capacitors next to the IC between the 12V positive and GND. \$\endgroup\$ – Wired365 May 31 at 20:32
  • \$\begingroup\$ Actually, initially I was confused as how to how something can act as a current source if the power transistor is being switched without an inductor (whcih would be the case if it was open-loop). But that was assuming the opamp was open-loop and acting as a comparator, but looking at it again, it's not actually open-loop. Not sure if this is the source of the problem, but you might benefit from some filtering capacitors in your current sense portion to ignore high frequencies. \$\endgroup\$ – DKNguyen May 31 at 20:33
  • 1
    \$\begingroup\$ When you use FET's in Falstad remember to add Cgd. Even 1pF would cause the Sim to oscillate. The β term is ~ 1/RdsOn. Using it as a comparator, one should expect oscillations from any delay without adding compensation \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 1 at 2:21
3
\$\begingroup\$

Your simulation program looks like it's modeling ideal op-amps.

  1. Real op-amps have phase shift around their loop-closure frequencies. You cannot cascade them without compensation.
  2. Real op-amps have finite output impedances in open-loop (600\$\Omega\$ is a nice round number, but it varies). Real FETs have finite gate capacitances. These gang up with each other to make even more phase shift when you have a FET in a current-source configuration like this.

You must have external compensation. Something like what I've shown. The amp-to-fet resistance should be around 200-1000 ohms. The RC time constant of the other resistor and the added cap should be, roughly, 10 times RC time constant of the anticipated gate capacitance times the amp-to-fet resistance.

Some experimentation will be necessary, or simulation on an accurate simulator.

enter image description here

\$\endgroup\$
  • \$\begingroup\$ I have been bit by exactly this as a hobbyist more than once. There's a pole formed from the rout of the opamp and cgs of the fet as well as another dominant pole in the opamp. \$\endgroup\$ – jonk May 31 at 22:19
  • \$\begingroup\$ Yes. Complicated, in this case, by having two op-amps that are not each individually compensated. I think that this is the only spot that needs additional compensation, though. \$\endgroup\$ – TimWescott May 31 at 22:34
  • \$\begingroup\$ Yeah. I was thinking it wouldn't take much to make it oscillate. It is already bad enough with one opamp. Just seeing a naked opamp's (-) input like this gives me the willies. (My first experience with this was a supposedly "simple" adjustable voltage power supply using an opamp driving the gate of a mosfet without external compensation.) \$\endgroup\$ – jonk May 31 at 22:38
  • \$\begingroup\$ Shouldn't the RC be connected to the non inverting input ? \$\endgroup\$ – Mike Jun 1 at 6:56
  • \$\begingroup\$ @Mike. No. That stage needs to be slowed down. If you look carefully, you'll see that the input resistor and cap make that op-amp into an integrator, which provides a single dominant pole to the loop \$\endgroup\$ – TimWescott Jun 1 at 15:46
0
\$\begingroup\$

The problem with current source circuits is they are prone to oscillations at high frequencies. Part of the reason for this is parasitic inductance, the other half comes from the current source circuit.

You can do one of two things: - Estimate the parasitics of the physical circuit and put them in the model (you'll need a good model for the mosfet also). - Try to experiment with adding capacitance in the feedback loop and eliminate high frequency oscillation points. - Limit the bandwidth of the current source to less than that of the oscillations.

From what I know, with working with circuits similar to this (this one is more complex and not easy to analyze), I'd experiment with capacitance.
A good place to start would be to place capacitance between the negative terminal and the output of the current source op amp. If that doesn't work try the negative terminal and the positive terminal, then the negative terminal and ground.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.