# Which input of NAND is preferred and why? [duplicate]

Let A and B be two inputs of the NAND gate. Say input A arrives at the NAND gate later than input B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?

Edit: Input A arrives Later than Input B. To optimize delay in the NMOS section. how do you place inputs A and B.

• Is signal A attached to input A or input B? (In other words: please avoid reusing variable names) May 31 '19 at 21:08
• how do you know that one is closer to the output than the other? May 31 '19 at 23:35
• Notice the lower A will directly experience the Miller effect of its gate-drain overlap capacitance, thus a stronger drive may be needed. Jun 1 '19 at 1:44

If input A goes high but the source terminal of its NMOS transistor is not at ground then the effective $$\V_{GS}\$$ for that transistor is reduced by the existing voltage at the source, thus reducing $$\I_{DS}\$$.