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Let A and B be two inputs of the NAND gate. Say input A arrives at the NAND gate later than input B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?

Edit: Input A arrives Later than Input B. To optimize delay in the NMOS section. how do you place inputs A and B. enter image description here

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    \$\begingroup\$ Is signal A attached to input A or input B? (In other words: please avoid reusing variable names) \$\endgroup\$
    – Huisman
    May 31 '19 at 21:08
  • \$\begingroup\$ how do you know that one is closer to the output than the other? \$\endgroup\$
    – jsotola
    May 31 '19 at 23:35
  • \$\begingroup\$ Notice the lower A will directly experience the Miller effect of its gate-drain overlap capacitance, thus a stronger drive may be needed. \$\endgroup\$ Jun 1 '19 at 1:44
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I would place input A closer to the output. If input B switches first then the bottom NMOS transistor has time to bring the source capacitance of the top NMOS transistor fully to ground before input A goes high.

If input A goes high but the source terminal of its NMOS transistor is not at ground then the effective \$V_{GS}\$ for that transistor is reduced by the existing voltage at the source, thus reducing \$I_{DS}\$.

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  • \$\begingroup\$ You asked "so that both inputs...arrive at the same time" but you don't control when the inputs arrive. I don't understand what you mean by "reduce the input delay A". I'm sorry but your comments don't make sense to me. \$\endgroup\$ Jun 1 '19 at 12:49
  • \$\begingroup\$ When (the bottom NMOS transistor has time to bring the source capacitance of the top NMOS transistor fully to the ground before input A goes high.) So, total Vdd is grounded and more Ids? second case: Vgs = vdd-vt and reducing Ids? \$\endgroup\$ Sep 4 '19 at 3:31

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