I need to connect current sense traces from a shunt resistor to my PMIC on the other side of the board. Due to space constraints, I'd like the traces to pass through vias directly underneath the shunt resistor (option 1 below), rather than first exiting the side of the shunt resistor before going through the vias (option 2 below).

Are there any issues with doing so? I would normally length match the traces on both sides of the board (per option 2 below), but can't do so with option 1. Will trace matching on only one side of the board be sufficient?

Option 1: Trace vias directly underneath shunt resistor enter image description here

Option 2: Trace vias exiting shunt resistor before going through vias enter image description here

  • \$\begingroup\$ What currents will be flowing thru those narrow traces? just currents at the microAmp level? \$\endgroup\$ Jun 1, 2019 at 4:20
  • 1
    \$\begingroup\$ why do you think length matching is necessary at all? Are those traces voltage pickoffs, or is the sensed current flowing through them? \$\endgroup\$
    – Neil_UK
    Jun 1, 2019 at 4:21
  • \$\begingroup\$ @analogsystemsrf At the uA level. \$\endgroup\$
    – jars121
    Jun 1, 2019 at 5:04
  • \$\begingroup\$ @Neil_UK I figured the traces should be ~equal to minimise resistance variation between them? Sensed current flows through them to a current sense amplifier in the PMIC. \$\endgroup\$
    – jars121
    Jun 1, 2019 at 5:07
  • \$\begingroup\$ Why even have the traces? Just put the via on the pad? \$\endgroup\$
    – hekete
    Jun 1, 2019 at 7:04

2 Answers 2


Both layouts are sound.

You don't need length matching. The current in the current sensing traces is small, so the variation in the trace resistance will have a negligible impact. The raise times are relatively slow too.

Somebody in the comments proposed to place the vias inside of the pads.
Generally, unfilled vias inside pads are not advised. Or they have to be carefully thought through. In this case unfilled vias in the pads (not to be confused with filled via-in-pad) are acceptable, because the vias would occupy only a small portion of the pads.


Consider offsetting the vias and Kelvin connections:

enter image description here

The ohmic error will be small, and keeping it symmetrical helps.

This keeps the vias well outside of the soldermask openings for the pads, ensuring they won't steal solder. (The vias should be tented.)

I would say this offsetting is reasonable (i.e. still a close approximation of the ideal Kelvin connection) for connection points within say 10 or 20% of the centerline (say, in the "40-60% of pad width" range). The traces can also be diagonal to get closer to centerline, though this makes an ugly acute corner if pulled all the way up to the pad. (Traditionally called an "acid trap"; I see mixed reports on whether that's actually a problem anymore.)

Counter-indication: if the resistor datasheet says to avoid material underneath the footprint (keep-out area). In that case, Kelvin connections aren't really reasonable. (Which would be odd, but maybe it happens sometimes, who knows.) The next best option is simply connecting the inside corners of the pads, and the vias can go wherever (say, as in Option 2).

To be clear, length matching and differential pair layout are irrelevant; any current shunt used at frequencies where these would apply (i.e., 100s of MHz), would not be a shunt at all, but some kind of RF power divider structure (of which a shunt resistor is kind of a special case, when some impedance mismatch is allowed). The microstrip (or whatever) structures into and out of such a device would likely be clearly specified in the datasheet.

(It's rare that a shunt is good for much above a few MHz, beyond which inductance dominates; maybe pushing 100MHz when made with great care, and the inductance compensated with an inductive link or RC filter.)

Trace resistance doesn't need to be matched locally, and its impact can also be reduced arbitrarily by choosing a better current sense amp (i.e. one with lower input bias current).


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