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I read a article saying "Latch-based designs, however, have smaller dice and are more successful in high-speed designs in which the clock frequency is in the gigahertz" but I am unable to understand how latch based design can help in lower clock time period.

While latches allowed time-borrowing but it seems that total path delay should always be less than clock time period (Considering case where Negative level latch placed in between two posedge triggered flops)?

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    \$\begingroup\$ smaller than what and more successful than what? \$\endgroup\$ – Marcus Müller Jun 1 at 10:27
  • \$\begingroup\$ Smaller and more successful than FF's for High-Speed design \$\endgroup\$ – Shubham Gupta Jun 2 at 6:48
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First of all, a latch is physically smaller than an edge-triggered FF, so it saves on die area and therefore reduces routing delays in general.

Second, every time you use an edge-triggered FF, you add its setup time and propagation delay directly to the overall path delay. The latch allows you to "hide" the setup time and its propagation delay is less, resulting in a lower overall timing penalty. In exchange, you must use a two-phase clock scheme and follow additional restrictions on how you design your logic.

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  • \$\begingroup\$ Is it correct to say that a latch base design will have a little improvement in terms of clock period of FF based design (i.e. setup time and few ps/ns of propagation delay improvement) We don't create latch based designs because of timing analysis complexity associated with Latches ? Have you ever tried to use latches in any real Design ( other than clock gating) with allowing time-borrowing ? \$\endgroup\$ – Shubham Gupta Jun 2 at 6:57
  • \$\begingroup\$ I can't say that I've ever done that, because my work is mostly with FPGAs, which are completely oriented toward FF-based design. \$\endgroup\$ – Dave Tweed Jun 2 at 11:24

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