Why propagation delay is measured at 50% of the input and output waveform?

I didn't find the concept of propagation delay measured at a particular point on the waveform.

Where does a wave start and end, exactly? These points are unmeasureable. So we measure something we can see clearly.

Because 50% of Vdd is the trip-point of standard CMOS inputs. In addition, the drive strength of CMOS outputs is usually the same against Vdd and GND, so 50% is a good match for the output, too.

If you had e.g. Schmitt trigger inputs, you have to put more thought into where the input trip-point L→H and H→L are. They are different. But usually, 50% Vdd will be assumed, too, for the sake of simplicity. The propagation delay is still one value for one L→H→L input cycle. It becomes important if you only ever match on one transition type, which is often the reason why you have a Schmitt trigger in a circuit. Take care.

If you had open collector or open drain outputs, you have to put more thought into the drive strength on the L→H output transition. The driven capacitance comes into play.

• I don't think you can make a blanket statement that 50% is the trip point or that output drive is symmetric. This is certainly not true in CMOS VLSI design. – Elliot Alderson Jun 2 at 12:13

I think it's better to look at the necessity of measuring rise and fall times to understand where the value comes from. The exact value 0-50% in this case where rise and fall times are characterized is dependent on device physics but here I will try to describe it in terms of usecase. Based on the technology node these days more commonly this can also be transitions (30%-70%) of Vdd or (10%-90%) of Vdd to measure this based on gate threshold voltage required for the transistor to be ON, desired region of operation (eg: saturation).

To explain this, consider a simple example of a CMOS inverter below with a capacitive load at the output, when you apply L->H transition at input the H->L transition at the output is not instantaneous rather takes some time due to the capacitive charging time factor. This time is called fall time and is measured between as the time to go from 0V to 50% of VDD threshold. Similarly the rise time is also captured. These values are required since propagation delay itself is the average of rise and fall time. This delay at a higher level of abstraction is useful in determining the gate delay (in this case inverter) of combinational logic. It is very important to know these delays especially for sequential circuits to meet the setup/hold of flip-flops.

simulate this circuit – Schematic created using CircuitLab

• The schematic is a bit misleading as it only shows a cap to GND. For high frequencies, GND and Vdd are essentially the same. The cap should either go to Vdd/2 or there should be two caps. – Janka Jun 2 at 7:43
• The schematic was only to roughly illustrate the point of calculating propagation delays and the input/output transitions. – Rajesh S Jun 2 at 7:53
• @Janka It doesn't matter where the capacitor is connected (as long as it is a fixed voltage), it looks the same to the inverter output. – Elliot Alderson Jun 2 at 12:11
• Correct. That's why I wrote the schematic is misleading. C1 is connected symetrically, regardless if it's bound to GND or Vdd. – Janka Jun 2 at 12:15

If you have no other information about your system, then 50% is a reasonable default level. It's easy to measure, it's probably a fast-slewing point on the waveform, and it may be near something that you need.

If you do have more information about your system, perhaps the voltage levels that the input will respond at, then you should use those.