For a university project, I have to design and construct a very simple CPU including the ALU. In order to select between different data lines that go into the ALU(32-bit data line), I have thought of two different approaches.

Basically, the first method is using a multiplexer, For example, it takes in input from register file and instruction register and gives out the output. This was the method recommended to me by the professor, however this method seems to get very complex very quickly based on the size of the data buses, and the number of operations needed to be performed.

The second method I found was to use tri-state buffers along with a decoder. Rather than use a huge multiplexer, it only requires a decoder large enough for the number of operations. However, with this solution, I was warned that there could be timing issues, where during the transition of the decoder, two tri-state buffers could be simultaneously activated, which would cause a short-circuit. Is there any truth to this, and can it be avoided? This was the method that I thought was used inside most modern architectures, but I could be incorrect.

Also, how is there no timing violation in case of multiplexers

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    \$\begingroup\$ Are you implementing this in an FPGA, or with discrete components? \$\endgroup\$
    – Mattman944
    Jun 2 '19 at 16:43
  • \$\begingroup\$ I will be implementing it in an FPGA using verilog. I know it is easy to synthesize the mux based approach in verilog easily but is it efficient? \$\endgroup\$ Jun 2 '19 at 16:47
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    \$\begingroup\$ No muxes aren't efficient, but modern FPGAs have lots of gates. It is better to be inefficient than deal with the issues of tri-state buses (oscillating floating buses, etc). Some FPGAs don't even have internal tri-state capability. \$\endgroup\$
    – Mattman944
    Jun 2 '19 at 16:53
  • \$\begingroup\$ So even in actual manufacturing of chips Mux is preferred due to its reliability, Is that correct? \$\endgroup\$ Jun 2 '19 at 16:58
  • \$\begingroup\$ When National Semiconductor introduced TriState interfaces, about 1970, the world of computers underwent a wonderful speedup. The wired-OR interfaces were replaced with actively-driven buses. You might revisit history, by using a variant of wired-ORs. \$\endgroup\$ Jun 2 '19 at 17:07

A tristate bus IS a multiplexer, so there really isn't much difference.

A multiplexer is basically a layer of AND gates followed by a layer of OR gates.

With a tristate bus, you're eliminating the OR gates, but you're replacing the AND gates with the arguably more complex tristate buffers.

In most FPGAs, you can't actually have internal tristate buses. If you attempt to use them, the synthesis tool will either throw an error, or convert them to the corresponding multiplexer logic.

  • \$\begingroup\$ So what kind of approach is followed in industry where ASIC is done in which tristate buffers are possible. If tristate buffers can be used, can we go for it instead of multiplexers \$\endgroup\$ Jun 2 '19 at 18:45

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