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I'm transferring data from memory to a peripherial's register in an STM32 uC. For example take 20 bytes. I understand that after sending all the 20 bytes, the "Transfer Complete" interrupt will occur. My question is: between individual bytes (e.g. 4th and 5th) how does the DMA know when it is time to send the next byte? How does it adjust its speed?

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  • \$\begingroup\$ DMA is usually interrupt-controlled. So if you send memory to a peripheral, it will be controlled by some "byte transfer complete" interrupt strobe (well, it's not an actual interrupt in case of DMA, just a control signal). \$\endgroup\$ – Eugene Sh. Jun 4 '19 at 17:03
  • \$\begingroup\$ In the STM32 micros that I've worked with, the peripheral's "transfer complete" bit (under a different name, like TXE or RXNE) is connected to the DMA engine. This lets the DMA know that the peripheral is ready for a data transaction. \$\endgroup\$ – TimWescott Jun 4 '19 at 17:28
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This is a complicated topic. STM32 has a very advanced I/O ARM Cortex architecture. Peripheral devices are connected to "bus matrix" (or "switch fabric") via a set of "AHB/AXI" busses. Take a look at 1/4 of the STM32H750 block diagram:

enter image description here

Each bus has local hardware means to arbitrate the access to it, so this is one of the mechanisms that regulates the rate of atomic transfers. The other mechanism is built into FIFO (First In First Out) buffers associated with each DMA channel. Each FIFO usually operates by "watermarks", which indicate the fill level of the buffer. If the buffer reaches certain pre-configured level, DMA engine starts to transfer intermediate bytes; when the level drops, DMA temporarily stops. The other end of FIFO is filled by an interface to a peripheral device, which usually also has some buffers, and local hardware state machines provide the data transfer as conditions permit. So the DMA engine "knows" when to transmit intermediate data when a set of flags/semaphores along the long chain of interfaces when they give it "green light". Obviously no "interrupts" are involved in this chain of handshakes, this is the entire idea of DMA (aka "Bus Mastering"), only the end of entire transaction is signaled by an interrupt (or/and by a status flag), so a software can reload the DMA pointers.

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It works both ways. When receiving, the peripheral signals the DMA controller it should read a byte. When transmitting, the peripheral signals to DMA controller when it should write a byte.

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