Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge?

The clock to capture flip flop is delayed by 60ps from the launch flop. The time period be 100ps. And the data path delay is 30ps. Setup and hold is 10ps both.

In this case the launch flop launches data at 0ps, the data come to capture flop after data path delay of 30ps. The 1st clock edge of capture flop occurs at 60ps.

Now data available at D pin of capture flop at 30ps and hence setup timing is met.

And now the next data will be launched by launch flop at 200ps. At 200ps, hold for the capture flop will also be met. So this condition is possible or i am missing out something?


  • \$\begingroup\$ Is that not what a D_FF does? can you provide waveforms, or better description, to illustrate what you mean? \$\endgroup\$ Commented Jun 5, 2019 at 3:38
  • \$\begingroup\$ I have edited the question. Can you please clarify. \$\endgroup\$ Commented Jun 5, 2019 at 5:39
  • \$\begingroup\$ This is called having different clock phases in your design. You would normally not just rely on propagation delay to adjust the timing for the different flip-flops. Instead you might use a positive-edge triggered FF for the first logic and a negative-edge-triggered FF for the second logic. Or make a clock management circuit that outputs clocks with edges at t=0, t=0.25T, t=0.5T, t=0.75T. Or whatever you need for your particular system. \$\endgroup\$
    – The Photon
    Commented Jun 5, 2019 at 5:52
  • \$\begingroup\$ yea possible...But then it would be called a "hold violation" in a normal system synchronous ckt operation. However in source synchronous ckts, this is used often. \$\endgroup\$
    – Mitu Raj
    Commented Aug 29, 2019 at 4:53

1 Answer 1


There are two situations to consider, D-flops closely coupled to each other on a board, and a D-flop each end of a long interconnect.

With the first, careful examination of the minimum propagation delays and the hold times usually results in it being OK to simply connect the clock to all D-flops. Q data stable at the active edge will usually remain stable long enough (non-negative) to meet the (often zero) hold time of the receiving flop. Being tightly coupled on a board means that little further skew occurs between clock and a data.

With a long interconnect however, we cannot rule out clock and data skew, and being either side of zero is not good enough. We need to generate two clock phases, one to capture the stable data in the receiver, and the next a guarranteed time later to clock the source, so that the source data hold time is met.

This is usually done by inverting the clock signal, and using one polarity for the source, and the other for the receiver. This is robust against varying the clock rate, and doesn't need any timing components. It is however very conservative on timing, as you often struggle to meet propagation and setup, and meet hold time with ease.

It's my personal opinion that it's probably better to think in terms of extending the hold time of the source data, rather than trying to meet the receiver's setup time. This is because most hold times are zero, so you only have to extend it further a little to meet your interconnect skew. You then have nearly all of the clock period available for propagation and setup. Of course, you still need to do worst case addition of all delays to make sure both setup and hold are met, you're just starting off from a different mindset.

  • \$\begingroup\$ Thanks a lot 👍😊 \$\endgroup\$ Commented Jun 5, 2019 at 8:29

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