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I am starting to design one of my first instances where I think impedance matching/ reflections might be an issue.

I want to daisy chain a clock from four seperate PCBs with a distance between PCBs of 2m using this 2MHz clock and this clock buffer to allow four separate PCBs to be synced to the same clock source.

I plan on using a four layer board, signal, gnd, power, signal with ground pours and vias.

Using the rule of thumb of 1/10 wavelength, at 2MHz the 1/10 is 149m, which is well below my 8m distance but I would rather tread on the safety side:

  1. I used this trace impedance calculator aiming for 50 ohm impedance. Is this the right impedance to aim for? Is this calculator suitable for my four layer stack up? enter image description here
  2. Development boards, such as this one , seem to use SMA connectors, but in the interest of reducing BOM cost and number of cables is there a signal connector that can be used for this differential cabling at this frequency. I cannot find one spec'd for this application or maybe because of the 'relatively' low frequency it doesn't a special cable. I am currently thinking, shielded with a differential pair but the cable with 50 ohm characteristic impedance.

Any help would be greatly appreciated!

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Using the rule of thumb of 1/10 wavelength, at 2MHz the 1/10 is 149m, which is well below my 8m distance but I would rather tread on the safety side

The rule of thumb is broadly correct but you analysis is poor. A clock signal is virtually a square wave and a square wave contains an infinite number of harmonics so, in order to preserve the clock's square (ish) shape you need to ensure that harmonics are considered and not the fundamental frequency of 2 MHz.

Maybe you can get away with the 7th harmonic or maybe it's the 9th, 11th, 13th or fifteenth. You have to decide what you think is about right. If you choose the fifteenth harmonic then the cable distance drops from 149 metres to about 10 metres. Other points: -

  1. The buffer you have chosen is well over-the-top and this is not needed. A decent CMOS buffer will do the job.
  2. The trace impedance calculator looks fine - model the line with respect to an inner ground/power layer.
  3. Virtually any decent connector will do the job
  4. Differential clock signals are much more preferable because of emissions problems with single-ended clocks
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Design to handle the RISETIME and the FALLTIME of the clock, unless its a pure sin-wave.

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