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In my FPGA designs I often deal with components which perform some kind of task/calculations which takes multiple clock cycles (non-pipelined). These components have an input port iStart which tells the component to start processing and similarly an output oDone which signals that the component is finished. This oDone output is then often connected to one or multiple iStart inputs of following components.

I'm often struggling with how I should design the trigger behavior of this signal, i.e., should it be edge triggered (rising edge triggers processing, signal usually high for multiple cycles) or level triggered (high level triggers processing, signal must be high for single clock cycle only). Sometimes these styles are mixed throughout the design (components written by different people) which leads to incompatibilities/bugs.

I used to write my components edge triggered because it allows combining multiple outputs using logical AND (if the outputs go low again at the correct time). Now I think the level triggered approach is probably better because the time point when the signal goes low again is clearly defined. For best compatibility it’s probably best if the inputs continue to use an edge detection, but the output is only high for a single clock cycle. What are your thoughts and recommendations on these styles?

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  • \$\begingroup\$ This is on the verge of being either "too broad" or "primarily opinion-based". Can you narrow your question down to a specific use case, or maybe a few closely-related cases? \$\endgroup\$ – Dave Tweed Jun 5 '19 at 11:30
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As long as you stay in one clock domain, this is either completely case-dependent, or up to your own taste. There will be cases where one is is better, but no general rule of thumb. In many others, it just won't matter. What you should avoid, though, is mixing them for no reason.

The picture changes when you cross clock domains: then you should try to use edge-triggered starts. Either with handshaking, if you require backpressure, or just feedforward. Toggle signals are easier to synchronize to other clock domains.

That said, I'm not a fan of only using the rising edge on an edge-triggered start signal. I generally use both edges, either one inducing a start, which allows me to just put a few registers (and a few synchronizers) and compare the last two. It makes both the possible launching and interpreting logic easier. Of course this is only possible if both the launching and receiving blocks are reset at the same times.

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