In my FPGA designs I often deal with components which perform some kind of task/calculations which takes multiple clock cycles (non-pipelined). These components have an input port
iStart which tells the component to start processing and similarly an output
oDone which signals that the component is finished. This
oDone output is then often connected to one or multiple
iStart inputs of following components.
I'm often struggling with how I should design the trigger behavior of this signal, i.e., should it be edge triggered (rising edge triggers processing, signal usually high for multiple cycles) or level triggered (high level triggers processing, signal must be high for single clock cycle only). Sometimes these styles are mixed throughout the design (components written by different people) which leads to incompatibilities/bugs.
I used to write my components edge triggered because it allows combining multiple outputs using logical AND (if the outputs go low again at the correct time). Now I think the level triggered approach is probably better because the time point when the signal goes low again is clearly defined. For best compatibility it’s probably best if the inputs continue to use an edge detection, but the output is only high for a single clock cycle. What are your thoughts and recommendations on these styles?