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Nios II is all about customizing, the essence of a softcore. Custom instruction is an interesting feature of the Nios II.

Custom instruction involves 2 inputs dataa and datab. Does this mean that it is not possible to create SIMD type custom instruction? Can the register file of a Nios II processor be extended so it can be shared with an SIMD type instruction?

Note: Purpose is to hardware accelerate image processing algorithms with a Nios II.

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Yes, it bypasses the ALU and there is a container for inserting your own logic to operate on instructions. If the data size is similar, it should be possible to create any logic you want as long as it falls withing the timing and data witdh of the NIOS custom instruction. Check the site on custom nios instructions

Nios II custom instructions are custom logic blocks adjacent to the arithmetic logic unit (ALU) in the processor’s datapath.

When custom instructions are implemented in a Nios II system, each custom operation is assigned a unique selector index. The selector index allows software to specify the desired operation from among up to 256 custom operations. The selector index is determined at the time the hardware is instantiated with the Platform Designer or Platform Designer (Standard) software. Platform Designer exports the selection index value to system.h for use by the Nios II software build tools.

Source: https://www.intel.com/content/www/us/en/programmable/documentation/cru1439932898327.html

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    \$\begingroup\$ custom instruction has 2 inputs and 1 output. This cannot be used to create a hardware accelerated 8x8 discrete cosine transform. \$\endgroup\$ – quantum231 Jun 6 at 21:07
  • \$\begingroup\$ You could, but you couldn't do it in one clock cycle, you would have to load up the values in chunks \$\endgroup\$ – Voltage Spike Jun 6 at 21:09
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    \$\begingroup\$ See in a 2D DCT, we have 2 8x8 arrays, and the output is 1 8x8 array. Do you really think this can be implemented in the way you are describing? \$\endgroup\$ – quantum231 Jun 6 at 21:47

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