I am in the process of making a prototype PCB with an Altera Cyclone IV or V FPGA and 2 channels of external memory, one channel for a softcore CPU and one channel for a 2d graphics accelerator. I would like to use DDR1 or DDR2 memory but at this point in the design I can use any form of DRAM, This is just a hobby project; there are no real constraints on the design. If I have to use slower memory, I will just run a lower screen resolution. I have a some questions about interfacing with external memory that I need to have answered before I can finalize my design.

  1. I have looked at a few reference designs to get a feel for what I need to do. These designs use DDR1 and DDR3 memory, the boards didn't seem to have any termination resistors besides the ones on the differential lines. Is this normal if the traces are short and you program the FPGA and memory with the correct drive strengths and the traces are properly impedance matched? Or are they using on chip termination?

  2. As far as I know, DDR1 doesn't have on chip termination, Is it safe to wire it directly to an FPGA without termination resistors as other designs have done?

  3. Are you required to supply a voltage reference to the FPGA Vref pins and the DDR Vref pins or just the DDR Vref pins?

  4. If you are required to supply a voltage reference to the FPGA, how many Vref pins per bank do you need to drive?

  5. When doing my initial routing on a test board, all of my DDR1 traces are close to the same length, Is it ok to just length match them all to the exact same length or is some requirement that doesn't allow that?

  6. If all of this turns out to be too complicated I can fall back to old fashioned SDRAM. I assume that with SDRAM you can just use any I/O pins, not just the dedicated high speed memory interface (DQ/DQS) pins on the FPGA?

  • \$\begingroup\$ A lot of these questions can usually be answered via the memory's data sheet... \$\endgroup\$ – MadHatter Jun 9 '19 at 14:46
  • \$\begingroup\$ Yeah I was hoping to find the answers to these in the datasheets but I have spent dozens of hours reading all sorts of datasheets for the fpga and the memory over the past week or two but I haven't found an answer to any of these questions still. I am hoping somebody out there has the answers that I can't seem to find. \$\endgroup\$ – BinaryLust Jun 9 '19 at 23:19

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