I have the following N-JFET DC circuit for which I must find the output voltage \$V_{out}\ = V_D\$ (the drain voltage with respect to ground) when a PWM signal from \$-10V\$ to \$0V\$ is applied to gate. I can solve the circuit when the signal is at \$-10V\$ so I will focus exclusively on the \$0V\$ part.

The circuit is simulated with the PWM signal at \$0V\$ applied to the gate of the JFET, thus explaining the connection between the gate and the source to ground.

enter image description here

I know that \$I_{DSS} = 10mA\$ and the pinch-off voltage \$V_p = -4V\$ and I found that when the PWM signal is at \$-10V\$ the JFET is blocked so \$V_{out} = 10V\$, but I don't understand how I can find the output voltage when PWM signal is at \$0V\$.

I found that if \$V_{out} = |V_p|\$ when \$ V_{GS} = 0V \$ then \$ I_D = I_{DSS}\$, but doing so would result in an impossible voltage drop of a hundred volt on my \$10k \Omega\$ resistor, so I conclude that \$V_{out}\$ must be less than this, thus my JFET should be somewhere in the ohmic region. However, I cannot find the value given by the simulation.

Other given values are \$\lambda\ = 0V^{-1}\$ for the channel length modulation parameter and a temperature of 25 Celsius degree.

Any help would be greatly appreciated.

  • \$\begingroup\$ Where does the input signal connect? At the moment, your schematic shows gate and source connected to ground with no provision for an input. \$\endgroup\$
    – Andy aka
    Commented Jun 10, 2019 at 10:26
  • \$\begingroup\$ Thank you, I added the clarification in the main post. \$\endgroup\$ Commented Jun 10, 2019 at 12:30
  • \$\begingroup\$ I suggest you look at the definition of JFET IDSS (it may not be what you think). \$\endgroup\$ Commented Jun 10, 2019 at 12:40

1 Answer 1


I think I got it.

Since I established the JFET works in the ohmic region, its resistance \$R_{DS}\$ can be approximated by assuming that \$I_D(V_{GS})\$ is linear in this region and so \$R_{DS} \approx \frac{|Vp|}{I_{DSS}} = 400\Omega\$.

The equivalent resistance of this circuit will be \$R_D + R_{DS} = 10k\Omega + 400\Omega = 10.4k\Omega\$ and the drain current \$I_D = \frac{V_{DD}}{R_D + R_{DS}} = \frac{10V}{10.4k\Omega} \approx 961.54\mu A\$. There is a difference of less than two percents between this current and the one given by the simulation, leading me to conclude this should be correct.

Thanks Peter Smith for pointing me to the definition of \$ I_{DSS} \$.


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