Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed.
In the Intel ALTPLL (Phase-Locked Loop) IP Core User Guide -> Expanding the PLL Lock Range is only a description how to maximize the input lock range but that doesn't affect the output clock. Do I have to combine the expanded pll lock range with the Zero-Delay Buffer mode or any other operation mode to achieve this?
The phase shift is a fixed value that is assumed to be less than 45 degrees. Right now I don't have the exact angle for the phase shift.