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Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed.

In the Intel ALTPLL (Phase-Locked Loop) IP Core User Guide -> Expanding the PLL Lock Range is only a description how to maximize the input lock range but that doesn't affect the output clock. Do I have to combine the expanded pll lock range with the Zero-Delay Buffer mode or any other operation mode to achieve this?

EDIT

The phase shift is a fixed value that is assumed to be less than 45 degrees. Right now I don't have the exact angle for the phase shift.

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  • \$\begingroup\$ you should specify the order of the phase shift you want, since you are talking about using PLL I assume you need a phase shift that requires a frequency higher than the normal operating frequency of the FPGA to even implement. So people knowing how much of a phase shift you want will help people answer in my opinion. \$\endgroup\$ – Juan Jun 11 '19 at 8:10
  • \$\begingroup\$ @Juan Right now I can't determine it exactly. But I assume that it will be less than 45°. I just want to figure out if I can use the PLL IP block. \$\endgroup\$ – Olupo Jun 11 '19 at 8:26
  • \$\begingroup\$ Most PLLs acheive this with a fixed 90 degrees phase shift. \$\endgroup\$ – Andy aka Jun 11 '19 at 8:32
  • \$\begingroup\$ @Andyaka But what if the PLL has a fixed phase shift unequal 90°? \$\endgroup\$ – Olupo Jun 11 '19 at 8:38
  • \$\begingroup\$ You asked: "but with a phase shift" and I said most operate at 90 degrees. Then you comment as per above and I say: what relevance has that comment to your original question. \$\endgroup\$ – Andy aka Jun 11 '19 at 8:41
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The lock range is dependent on the VCO inside the chip. altpll allows you to tweak the PLL VCO lock to a larger capture range than usual. I would not expect more than about a 2:1 range however.

Output phase shift is independent of this. Phase shift is generated by the PLL output divider logic choosing different digital delays on the output referenced to the VCO frequency. Therefore the phase you select will track with the VCO frequency, and thus, will follow your input if you're choosing a net 1:1 clock ratio.

So if you configure the PLL for a 45-degree shift and a capture range of 50 to 100MHz, there will be 2.5ns delay at 50MHz output and 1.25ns at 100MHz output.

You will also need to make sure the PLL is in a zero-delay, or even better, external feedback mode so that the delay can track the input more precisely without skew.

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  • \$\begingroup\$ I think the range will be a problem. It will be between 20MHz to 200 MHz. Right now I have other issue to solve first before I can come back to the PLL issue. \$\endgroup\$ – Olupo Aug 19 '19 at 7:10
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I'd try only with those devices that have a hard IP block for dynamic PLL reconfiguration unless the input clock has a narrow frequency range.

A PLL that expects to generate 10 MHz from 10 MHz will probably lock against a 10.1 MHz source and keep the programmed output phase shift (because as far as the PLL is concerned, the input clock is the reference clock), but I'd be less optimistic that you could lock onto a 20 MHz clock with the same settings.

Reconfiguring the PLL from a hard IP block would write the same internal registers as loading a bitstream, so if you have a rough idea of the expected frequency, you can set that up in the PLL, and leave the fine matching to the feedback loop.

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  • \$\begingroup\$ Reconfiguration is a good point. Just found PLL reconfig IP block. I'll test it within the next week. The input frequency range is a little bit broader. I think we will a range from 20 to 200 MHz. \$\endgroup\$ – Olupo Jun 20 '19 at 11:56

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