Instantiating module in condiotional block verilog

Question

Considering a module cannot be instantiated inside if block, how are we supposed to instantiate the module outside the if-else block, keeping in mind that the inputs given to module in if and else blocks are different?

Problem:

if(sel==0)
  moduleex s1(inp1,out);
else
  moduleex s2(inp2,out);

What is the legal way to write this logic in proper Verilog syntax?

Answer 1

That's easy — put the multiplexer outside the module:

assign inp = sel ? inp2 : inp1;
moduleex s1 (inp, out);

You can even do it all in one line if you're so inclined, but this tends to be less readable:

moduleex s1 (sel ? inp2 : inp1, out);

Answer 2

You can use the ternary operator:

wire out_s1;
wire out_s2;
wire out;

moduleex s1(
    .in(inp1),
    .out(out_s1));

moduleex s2(
    .in(inp2),
    .out(out_s2));

assign out = (sel == 0) ? out_s1 : out_s2;

The last line means IF sel IS 0 THEN use out_s1 ELSE use out_s2.

Answer 3

Wait a sec... the question is asking about conditional instantiation of two different instances of moduleex: s1 or s2. Conditional instantiation is a compile-time option, not a procedural like ‘if’. Conditional instantiation is something you do with `ifdef or genvar - only once, when the logic is compiled.

Unfortunately, hardware being what it is, to model what is being asked - selecting between one instance and another - you have no choice but to create both instance s1 and s2 before the ‘if’ statement, then modify the ‘if’ to select the output of one instance or the other. That’s shown above, but I wanted to make clear that’s the reason why.

Now, having done that, if for some reason the variable sel never changes (e.g, with an assign) then synthesis might prune away the unused moduleex instance. But nevertheless both instances of moduleex still need to be declared before the selecting ‘if’, they can’t be declared in it.

The answer that shows modifying the variables to one instance - while correct - misses the point.