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I am wokring on a board that uses Micron 1Gb QSPI (mt25qu01gbbb8e12-0aat) to load configuration on to FPGA at power on.

As per the datasheet of QSPI (https://www.micron.com/-/media/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf), it says STR max supported frequency as 166Mhz. (Time Perios - 6.02ns)

In the Serial IO timing diagram, they mention that the Clock to Output Valid Delay (Tclqv) for 10pF is 5ns.

If the delay on QSPi data output itself is 5ns, is it possible to have the QSPI boot working at max speed of 166Mhz taking into consideration setup time requirements of FPGA and propagation delays on pcb

I am confused if I am reading the timing diagrams incorrectly and not understanding what the Tclkq 5ns delay is for.

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Maybe. It depends on how fast the FPGA is, how you are clocking the serial flash memory, and how your interconnects have been designed. You can't answer a question like this by considering the characteristics of just one component.

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  • \$\begingroup\$ Hi Elloit, thanks for your prompt response. Based on the FPGA data sheet, it has a setup time of 3ns for the SPI data pins and the board propagation delay is about 1.2ns \$\endgroup\$ – pmuppala Jun 11 at 22:39

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