3
\$\begingroup\$

I am wokring on a board that uses Micron 1Gb QSPI (mt25qu01gbbb8e12-0aat) to load configuration on to FPGA at power on.

As per the datasheet of QSPI (https://www.micron.com/-/media/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf), it says STR max supported frequency as 166Mhz. (Time Perios - 6.02ns)

In the Serial IO timing diagram, they mention that the Clock to Output Valid Delay (Tclqv) for 10pF is 5ns.

If the delay on QSPi data output itself is 5ns, is it possible to have the QSPI boot working at max speed of 166Mhz taking into consideration setup time requirements of FPGA and propagation delays on pcb

I am confused if I am reading the timing diagrams incorrectly and not understanding what the Tclkq 5ns delay is for.

enter image description here

enter image description here

\$\endgroup\$
0
\$\begingroup\$

Maybe. It depends on how fast the FPGA is, how you are clocking the serial flash memory, and how your interconnects have been designed. You can't answer a question like this by considering the characteristics of just one component.

\$\endgroup\$
  • \$\begingroup\$ Hi Elloit, thanks for your prompt response. Based on the FPGA data sheet, it has a setup time of 3ns for the SPI data pins and the board propagation delay is about 1.2ns \$\endgroup\$ – pmuppala Jun 11 '19 at 22:39
0
\$\begingroup\$

No, 166MHz is not really possible to achieve with a normal clocking setup. As you have already found, the sum of Tclqv + PCB delays + QSPI master input/output delays will be your limiting parameter.

With a standard QSPI master you can rarely reach higher than 80MHz.

A QSPI master with feedback clock capability can probably reach about 100~120MHz. Feedback clocking compensates for PCB delays and delays in the input/output pins of the QSPI master.

In order to reach 166MHz, your QSPI master must implement full adaptive clocking, where the sample clock is dynamically phase-shifted to align with the actual DQ signals from the flash memory. Thus compensating for PCB delays, input/output delays in the master, as well as the Tclqv delay. This is similar to the auto-leveling mechanism used in DDR3 SDRAM memories.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.