# How to scale down voltage of the the video signal without affecting input wire impedance

This is a question stemming from this one where I search for the root cause of AD725 displaying wrong colors. Current step have shown that I must be out of the spec for the input of the chip: my RGB video signal is 1 Vpp (while AD725 accepts max 0.741 Vpp - and that's why CXA1645 shows perfect pic and AD725 may go crazy).

Here's one of the RGB signals, measured on the AD725 pin after decoupling capacitor. There's DC bias of about 3V before the cap. I can follow the reference circuit in the datasheet on page 12 lower part putting 470 pF caps in series on input and making opamps gain of 0.741 and putting decoupling caps on outputs which are to be connected to AD725. But:

• prefer +5V or +12V supply only circuit;
• can not find AD8073 or similar opamp available to use;
• circuit must not affect input wires as much as possible (they go further to other parts of the board), thus this solution does not look good.

Is there any more suitable circuit to do the task? Dot frequency is 25 MHz (PAL/NTSC). There're 2SC1815 transistors in the video signal conversion circuit in one of the other circuits attached to RGB lines, thus these transistors may do the task.

I am strong in digital stuff, but must improve in analog...

• Did my answer answer make any sense to reduce amplitude with load. If your signal looked better , I might go into more detail. – Tony Stewart Sunnyskyguy EE75 Jun 12 '19 at 1:11
• Don’t worry about the load impedance perfect matching as much here, unless you have long cables with prop delay causing ghosting. – Tony Stewart Sunnyskyguy EE75 Jun 12 '19 at 2:34

Many triple video buffer ICs are available. These generally have a voltage gain of +2 to compensate for loss in the external output resistor when terminated. One example is the THS7314, which can handle up to 1.4Vpp on each input. 1V in produces 2V out. To divide this down to 0.7V you need a divider ratio of 2.0/0.7 = 2.86, so in the circuit below R1 should be (2.86-1) = 1.86*R2. The output impedance of the divider is R1 || R2, which is 1/(1/R1+1/R2) = 1/(1/1.86+1/1) = 0.65*R2. Therefore R2 = Zout/0.65.

The AD725 has high input impedance so the exact output impedance of the divider is not important, it just needs to be low enough for the DC restore clamps to work properly. If you choose the recommended 75Ω then R2 is 75/0.65 = 115Ω and R1 is 115*1.86 = 214Ω. The closest E24 values (5% tolerance) are 120Ω and 220Ω. In your related question the composite images do appear to be overdriven, so reducing the levels may help.

• AD725 sets DC bias for its inputs (and that's why 0.1 uF capacitors are put in there), your circuit will change this bias. There must be cap between divider and R/G/B pin, but I caught the issue: resistors in divider + series capacitor on the pin form RC network, they start oscillating and this oscillation flows into the luma output (at least - I am currently experimenting with luma), screen has annoying (moving) vertical lines. Furthermore, touching these resistors with hand (adding even small R/L/C into the network) causes image to corrupt even more. – Anonymous Jun 19 '19 at 19:48
• This circuit merely buffers and scales the signal. You should still include the 0.1uF coupling capacitors on the inputs to the AD725. – Bruce Abbott Jun 20 '19 at 0:19

The AD725 spec says it has 150 Ohm inputs and is usually matched to your source which must be 75 Ohm standard, so what R value will reduce the signal to the required level on each channel? But adding another 150 Ohms to ground would cut the signal presently from 2/3 to 1/2 compared to no load. That difference is 1/6= 16.7% which is not enough.

If 150/(150+75)= 1 Vpp.
Then what is R for ;
R//150 / (R//150 + 75) = 0.741 Vpp.

R//150 / (R//150 + 75) = 0.741 * 150/(150+75).

This is your challenge for analog and assumes you know Ohm’s Law and parallel R conversions.