# Counter and elementary logic gates

I need to create a counter that counts down from 59 to zero. For that, i created a simulation in Proteus software where i used 4510 IC as a down counter and created the following circuit.

Now, i thought that, since this 4510 IC, when working in down counting mode, has output Co at logic zero whenever it reaches zero value, that means that when both of these two ICs have Co=0 then, i need to reset them to required value, which is in my case 59, otherwise it would start from 99 downwards.

It works fine when the circuit starts, because it actually starts at 59 and goes down all the way down to 10 and then, instead of going down to 9 it resets to 59, which is not what should've happened, since both Co's should be low when i have 00 combination at the output.

Does anyone have an idea what could be the problem here? Any help appreciated!

• Are the reset lines really floating? Jun 12, 2019 at 15:35
• Yes,i ve actually set them to zero right after i posted this, it changes nothing Jun 12, 2019 at 15:37
• I don't see the reason for U14, I think an inverter from U12's !CO was enough; I'd put the As to fixed levels rather than leaving them open and connecting them to U14... Jun 12, 2019 at 15:41
• @aschipfl Inverter is actually good idea, however, result is the same as before, it resets after 10 Jun 12, 2019 at 15:48

There is a note about this in the original RCA (now TI) datasheet: OR, Your problem occurs in the transition between 10 and 09, when there is valid CO activity for both counters. It could be that in the Proteus model, one CO is going low before the other has a chance to return high, a race condition.

Either way, very small R-C networks between the CO outputs and the NOR gate will filter this glitch. I would start with a 1 us time constant, like 100 ohms and 10 nF.

• 1 us time constant doesnt work, it resets at 52 then Jun 12, 2019 at 15:45
• I tried reseting (or preseting, since PE is what i am activating) using exactly CD4071 with an inverter and it works just fine! Jun 12, 2019 at 15:56

The problem is that the PE input operates asynchronously with respect to the clock, and the small glitch that occurred at the 10 → 9 transition activated it.

You could add another gate so that the PE input is only activated when the clock is low. Then the clock being high will mask the glitch.

However, this creates a different problem: the 00 state will only last for half a clock, and so will the 59 state. If it doesn't matter to your application, you could change the preset value to 60, then your counter would go

  ____      ____      ____      ____       ____      _
_/    \____/    \____/    \____/    \_____/    \____/
_ _________ _________ ____ ____ _________ _________ _
_X___02____X___01____X_00_X_60_X___59____X___58____X_


Note that there's still the danger that this kind of "glitch" reset might not reliably reset both counters.

Otherwise, you need to switch to a different counter that has a truly synchronous load function.