I'm reading Power Bus Decoupling Guidelines for Printed Circuit Boards with Widely Spaced Power Distribution Planes.

And they have these recommended connection configurations for bypass capacitors placement relative to the bypassed component:

4 layer board bypass capacitor placement recomendations. Source: learnemc.com

The first case where both the component and the capacitor are on the same side I think I understand why the component's and capacitor's connections to power plane 2 are closely spaced. This should be to minimize the inductance of the component's power pin's connection to the bypass capacitor. And this low inductance is important for supplying the component's internal as well as I/O current surge demands.

But I'm not getting the reasoning for the second case with the component and capacitor on the opposite sides of the board. Why is this different connection configuration needed? It seems this adds extra distance for the currents to travel increasing inductance. Why wouldn't one connect the adjacent pins of the capacitor and component to the same power plane?


It is because in the second case the current travels down each via in OPPOSITE directions. Assuming that:

  1. the vias are placed right beside each other, and...
  2. that the currents are equal (i.e. the capacitor is only decoupling only that component pin and the component pin is only being decoupled by that capacitor),

then the magnetic fields generated by each current would be equal and opposite, mostly cancelling each other out thereby reducing the effective inductance.

Now that I've said that, note that this is also the case for the long vias in the first example. The take-away here is the cancelling magnetic fields of the currents in the long vias (which would otherwise have higher inductance) is not unique to widely spaced power plane PCBs. The inductance due longer traces in the the horizontal distance is true for any board, not just wide spaced planes so that's not what the book is trying to communicate to you.

You get a similar effect by placing the two vias going to the power and ground plane for a decoupling capacitor on its side (so that they are closer together) rather than its ends. That's interesting. I've never thought it in terms of the vias between two separate components, just for a single component.

See: Decoupling cap routing on a 4 layer PCB

That's interesting. I've never thought about it in terms of vias between two components. Only ever between one component.

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Another way of saying what @DKN has written correctly, is the goal of a decoupling cap is to :

  • minimize the area enclosed by the loop current for a pulse with fast rise time.
  • minimize trace inductance (~0.5nH/mm)
    • two inductive vias (~1nH) close together sharing the same current pulse in opposite directions will have some mutual inductance that tends to reduce the sum of each L towards but never completely cancelling.

Both these arrangements accomplish this, whereas swapping any pairs would be worse in both criteria above.

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  • \$\begingroup\$ Would it be correct to say for the top configuration with the component and capacitor on the same side that the connection from ACTIVE DEVICE to Power Plane 2 has higher inductance then from ACTIVE DEVICE to Power Plane 2 and back up to CAPACITOR? \$\endgroup\$ – axk Jun 13 '19 at 0:09
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    \$\begingroup\$ no, Mutual coupling is not high enough to reduce L1+L2 by 50% due to pad size and via spacing. But it is correct to say the inductance of both vias is less than if they were far apart and also that creates a loop area in the dielectric with a Zo of each via such that Zo >> ESR of the Cap but perhaps only for frequencies in the microwave (>300MHz) band so not good for that. If Zo of via is 40 Ohms and Cap ESR 40mOhms that degrades performance <1ns. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 13 '19 at 0:46

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