# CLK signal on DAT0 line on SD protocol?

I'm facing some problems in the initialization stage of the SD protocol on a custom board, specifically when sending the ACMD51 command and reading the Status Card register on the DAT0 line. I've noticed that, when the command fails, I see a duplicated CLK signal on the DAT0 line. The picture below shows the CMD line(magenta), DAT0 line(yellow) and CLK(cyan). The last pulse before the B cursor is the end bit of the ACMD51 command. As can be seen, the DAT0 line replicates the CLK while the command is transferring and even after the command is issued (just for one pulse).

I've looked in the specs and, from what I understood, DAT lines should be HIGH when there's no data for transferring or LOW for signaling busy, but I don't get what could be the meaning of that duplicated CLK, apparently sent by the card itself. Maybe I've missed some point on the specs. What could cause that oscillation on the DAT line?

• Do you mean magenta when you say cyan and do you mean cyan when you say blue? – Andy aka Jun 13 at 8:22
• Sorry, yes. I'll correct it. Thanks :) – perencia Jun 13 at 8:23