I understand the basics of blocking and non-blocking assignments in verilog. I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently using non-blocking statements.
My question is, why was non-blocking assignments included in Verilog. I can think of the following example to give weight to my statement.
Using blocking assignment:
always@(posedge) a = b; always@(posedge) c = d;
Using non-blocking assignments:
always@(posedge) a <= b; c <= d;
So the two pieces of code above carry out the same process (parallel assignment of b to a and d to c, ignoring the race condition in case of blocking assignment). Similarly, if we take the case of swapping two variables in verilog, it is possible to do it with both non-blocking and blocking assignments.
But I am not able to find some example which will showcase that it is not possible to do it with non-blocking assignment and can only be done with blocking assignments.
I hope somebody can throw some light on the same.
alwaysblock for each parallel signal assignment? I would say thanks, but no. \$\endgroup\$
a<=b; c<=a;? \$\endgroup\$