How can I improve my 3 decade counter design so that it counts sequentially in Verilog [closed]

Question

How can I improve my 3 decade counter design so that it counts sequentially?

I am attempting to build and simulate a 3 decade BCD counter by cascading 3 decades counters that produce an output to indicate when the count of 9 is reached.

My design works, in that it counts sequentially, apart from the times when any of the decade counters reach 9, as this instantenously triggers the next counter to start and instead of going from 008 to 009 or 018 to 019, my design goes from 008 to 019 or 018 to 029, respectively.

Please see extract of code below:

  module ThreeDec_Synch_BCDCounter(output [11:0] A, output y, input clk, reset);
  wire DQ1, DQ2;

  Synch_BCD_Counter SBC0({A[3:0]}, DQ1, clk, reset);
  Synch_BCD_Counter SBC1({A[7:4]}, DQ2, DQ1, reset);
  Synch_BCD_Counter SBC2({A[11:8]}, y, DQ2, reset);
endmodule

module Synch_BCD_Counter(output [3:0] A, output y, input clk, reset);
  wire w0, w1, TA1, TA2, TA3;
  wire Q0b, Q1b, Q2b, Q3b;
  supply1  PWR;

  and  #(1) g0 (TA1, A[0], Q3b);
  and  #(1) g1 (TA2, A[0], A[1]);
  and  #(1) g2 (w0, A[0], A[3]);
  and  #(1) g3 (w1, A[0], A[1], A[2]);   
  or   #(1) g4 (TA3, w0, w1);
  and  #(1) g5 (y, A[0], A[3]); 
  
  TFF2  T0 (A[0], Q0b, PWR, clk, reset);
  TFF2  T1 (A[1], Q1b, TA1, clk, reset);
  TFF2  T2 (A[2], Q2b, TA2, clk, reset);
  TFF2  T3 (A[3], Q3b, TA3, clk, reset);  
endmodule

Please also see waveform below:

I have tried about everything that I can think of to try to get it to work, but I am not having much success.

Therefore any asistance/insight that anyone can provide will be very much appreciated.

Answer 1

Since your code is for a learning exercise I will not give a full answer.

Synch_BCD_Counter should have 1 more input for enable. This input will replace PWR. It also needs to be added to various parts of your combinational logic, which I will leave to you to figure out.

The y output will become the enable for other Synch_BCD_Counter instances.

All instances should be using the same clock. In general, it is a bad practice to use output logic as a clock of other blocks (there are timing issues and other limitations).

Answer 2

The working solution that I was aiming for is shown below:

module ThreeDec_Synch_BCDCounter(output [11:0] A, output y, input en, clk, reset);
   wire DQ1, DQ2;

   Synch_BCD_Counter SBC0({A[3:0]}, DQ1, en, clk, reset);
   Synch_BCD_Counter SBC1({A[7:4]}, DQ2, DQ1, clk, reset);
   Synch_BCD_Counter SBC2({A[11:8]}, y, DQ2, clk, reset);
endmodule

module Synch_BCD_Counter(output [3:0] A, output y, input en, clk, reset);
    wire w0, w1, TA1, TA2, TA3;
    wire Q0b, Q1b, Q2b, Q3b;

    and  #(1) g0 (TA1, A[0], Q3b, en);
    and  #(1) g1 (TA2, A[0], A[1], en);
    and  #(1) g2 (w0, A[0], A[3], en);
    and  #(1) g3 (w1, A[0], A[1], A[2], en);   
    or   #(1) g4 (TA3, w0, w1);
    and  #(1) g5 (y, A[0], A[3], en); 

    TFF2  T0 (A[0], Q0b, en, clk, reset);
    TFF2  T1 (A[1], Q1b, TA1, clk, reset);
    TFF2  T2 (A[2], Q2b, TA2, clk, reset);
    TFF2  T3 (A[3], Q3b, TA3, clk, reset);  
endmodule

And an extract of the waveform is shown below:

Thanks again to all that contributed!!

Answer 3

A BCD counter consists of two clocks ClkA,B for two counters , one divide by 2 and the other divide by 5 .You only have one clock in. That was the approach used for TTL then BCD Decoded.

But for CMOS, they used the shifting 1's approach called a Johnson counter then BCD Encoded.

A 2 digit BCD counter also consists of 1 clock for each decade, with a Ripple Carry Out (RCO or CO) to clock the next digit when the 9 transitions to a 0.

When the count = “1001”=9, the decoded output and ClkA the next stage counts 1 and this stage is reset.

output Q1 = ClkB

Repeat for each of 3 stages and decide if you want the leading Zero's blanked then implement.

Lessons to learn.

Study existing designs in hardware, learn how the datasheets define specs, then do the same for your logic. Logic Tables, State Diagrams, Timing limitations, In/Outs etc. Decide if you need to optimize low level code or use libraries with higher level code.

Alternatively study best-in-class microcoder designs from scratch in trade journals , magazines, books, online SuperUser Forums. Avoid Mickey Mouse articles as examples of good design [practice] ... my mentors were young Prof's in Compilers etc in CSE in the late '70's and ever subroutine had a "HIPO paragraph" in preamble. (IBM term for Heuristic Input Process & Outputs.)

Example of a cascaded counter in hardware.. now replicate in software.

Using CD4026's (late 70's vintage CMOS)