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I have come across some text or blog before but I cannot find the source that: when we use 74HCT08 AND gate IC and for the logic inputs if we use pulldown resistors to prevent floating then we need to use the resistor pulldown resistor values Rp low such that the input should not rise over 0.9V.
Regarding a such input as hand drawn below:
Why does the value of resistor matter and how could high values make the input higher than 0.9V when the switch is open?
If you know nothing about CMOS, you need ohms law, a data sheet, and some common sense.
If you know something about CMOS, then just the common sense will do.
Per the data sheet, the input leakage current for a 74HCT08 is \$1 \mathrm{\mu A}\$. Per ohms law, this means we need \$R < \mathrm{\frac{0.9V}{1\mu A} = 900k\Omega}\$.
Common sense says that unless we're designing something for insanely low current consumption, and for which we can guarantee an electrically quiet environment, using the maximum resistance here is silly. So choose something convenient, like \$\mathrm{10k\Omega}\$.
A basic knowledge of CMOS says that for all practical purposes a CMOS chip's input current is nothing -- so you fall back on common sense, and you're done.
Note: that this is not the case for a lot of modern microcontrollers -- they are often designed so that without the pins being programmed, they have built-in weak pull-ups, to reduce current, and for historical reasons (see my final note, below). But sometimes they have built-in weak pull-downs on some pins, for practical reasons. So always read the data sheet.
Final note: If you were designing circuits 30 years ago, then the gate in question may well have been TTL. In that case, you would want a pull-up resistor (because TTL inputs source a bit of current, but sink less). Then you'd use the same \$\mathrm{10k\Omega}\$, but it would be to VCC. There is no reason not to do this for CMOS, and it's oh-so-slightly more comfortable for old circuit designers when they see it.
The basic rule is never leave CMOS inputs floating for EMI noise and ESD immunity reasons.
Thus a resistor to the opposite rail of the closed switch is used to shunt weak stray currents induced by external means. The lower, the R, the greater the immunity when the switch is open.
Schematics do not not show the length of the path to the switch, so the trace or cable ESL inductance and the mutual coupling to external current transients (B field) or the stray capacitance to high dV/dt E fields is unknown.
You must know the environmental noise voltage and impedance to choose how to design for immunity. The easiest way is a shunt resistor as shown. 10k is better. For lower micropower a better way is with a filter and shielding. If the switch is not gold plated (normally done if rated <2A) then you would eventually see intermittent contacts from a lack of wetting current.
The input to a CMOS logic gate typically has a specified leakage current of up to \$1 \mu\$A. If the resistor is 1 M\$\Omega\$ then the resulting voltage would be 1V, so in this case the resistor value is too large.
A large resistor value will also cause a slow fall time at the input, which can cause undesirable behavior.
