# Why it is said that second transistor cannot enter saturation mode in Darlington pair? When I made equations it came out that for both of transistors to be in saturation Vc-Ve2<.2V
Vc-(Vb2-.7V)<.2V
Vc-Vb2<-.5V ............{eqn a}
As for first transistor to be in saturation region
Vc-Vb2<.2V ............{eqn b}
If eqn a is satisfied then eqn b will automatically satisfied
.So both transistors should be able to go to saturation if eqn a is satisfied.

• Could you do us the favor of showing your mathematical reasoning instead of simply stating your own conclusions about it? (It might also help if you labeled your BJTs, too.) I'd rather see your reasoning and point out where you may have made a mistake, than try and develop my own reasoning that may not help you as much.
– jonk
Jun 16 '19 at 5:40
• look up schottky or Baker clamped transistor, the explanation for why they work might help you here. Jun 16 '19 at 5:56
• I have added 2 spaces at the end of each of your lines to prevent unintended line wrap. If you terminate a line with 0 or 1 space the language appends the next line onto the end of the current line. Adding two spaces at each line's end prevents this. Jun 16 '19 at 8:05

For an individual NPN bipolar junction transistor (BJT), the condition for saturation is

$$V_E < V_B > V_C$$

i.e., the transistor's base-emitter diode AND its base-collector diode must both be forward biased.

Applying Kirchoff's voltage law to the Darlington pair (fig. 1) we see that the voltage at its collector is

$$V_{Q2.C} = V_{Q2.E} + V_{Q2.BE} + V_{Q1.CE}$$

i.e., the voltage at Q2's collector $$\V_{Q2.C}\$$ is equal to the sum of Q2's emitter voltage $$\V_{Q2.E}\$$, plus the forward bias voltage across Q2's base-emitter diode $$\V_{Q2.BE}\$$, plus the voltage across Q1's collector-emitter path $$\V_{Q1.CE}\$$. Figure 1.

Noting that

$$V_{BE} := V_B - V_E$$

by inspection, for $$\V_{Q2.BE}\gt0\,V\$$ and $$\V_{Q1.CE}\gt0\,V\$$ we see that Q2 transistor in a Darlington pair cannot meet the requirement for saturation:

$$V_{Q2.E} < V_{Q2.B} \stackrel{?}{>} V_{Q2.C} \\ \Rightarrow V_{Q2.E} < V_{Q2.B} \stackrel{?}{>} (V_{Q2.E}+V_{Q2.BE}+V_{Q1.CE}) \\ \Rightarrow V_{Q2.E} < V_{Q2.B} \stackrel{?}{>} (V_{Q2.E}+(V_{Q2.B}-V_{Q2.E})+V_{Q1.CE}) \\ \Rightarrow V_{Q2.E} < V_{Q2.B} \ngtr (V_{Q2.B}+V_{Q1.CE})$$

Q2 approaches the transition point between forward active mode (small signal amplification) and soft saturation, but it never achieves saturation.

• Your notation is rather awkward. For example, the first equation could be: $V_{C2}=V_{E2}+V_{BE2}+V_{CE1}$
– Chu
Jun 16 '19 at 8:47
• I've added the above equation to your question, (to show the mathjax formatting).
– Chu
Jun 16 '19 at 9:18
• The annotation $V_{C2}$ is ambiguous; it could (and typically does) mean "the voltage across capacitor C2" in a schematic that has a capacitor C2. To avoid ambiguity I always expressly state the target part's full reference designation. Jun 16 '19 at 11:18
• How can it be ambiguous when there are no capacitors in the circuit? Normally, the first letter indicates what the variable is; Q looks like charge. Anyway, it's your answer, I'm just giving my opinion.
– Chu
Jun 16 '19 at 11:29
• ... also, you've used $V_C$ in the first inequality!
– Chu
Jun 16 '19 at 11:48

Even if Vce1= 0 V and Ic is low, Vce2 cannot be less than Vbe2 which is not fully saturated as a single transistor can be, yet hFE will be reduced. Therefore other configurations can be used. simulate this circuit – Schematic created using CircuitLab

Therefore you may say...

...that the Darlington transistor, as a switch, adds a diode drop to a single transistor Vce(sat).