I'm using the Right side PLL to implement a clock generator on a Mach XO2 7000 FPGA that takes in a 50 MHz clock generated by the Left side PLL and outputs a clock that can be changed from 50 MHz to close to 100 MHz by means of the Fractional-N functionality of the Right Side PLL. I'm aware that this is not a great solution in terms of jitter, but that's a tradeoff I'm willing to take. For that purpose I've used IPExpress to configure the PLL with these settings:
These settings should configure the PLL to generate a 75 MHz clock signal on the CLKOP output. But instead the PLL locks to the 50 MHz input signal, disregarding the Fractional-N settings. The Right side PLL is kept in a reset state until the Left side one locks. I'm also using a Wishbone interface to both PLLs and use it to configure the same settings onto the PLL and reset it afterwards but signal capture shows the PLL losing lock after the reset command is sent, with the CLKOP output low for ~20uS and then a frequency increase on the CLKOP output from around 10 Mhz to 50 Mhz, at which time the LOCK signal is set again. I can't find any examples of Fractional-N synthesis on this FPGA nor do I understand why it disregards the settings, as the IPExpress wizard shows the CLKOP frequency at 75 Mhz. Any thoughs on what might be the issue ?