I have the following circuit and i am trying to find uin/vout. My thought process is that M3-M4 is a Cmos inverter so i can calculate the gain until that point as A1= -gm3(ro3//ro5) How can i find the overall gain?
How it is self biased in every stage determines the gm of each stage which multiplies greatly from current mirror to complementary common source to drain follower then this open loop gain is limited by the feedback resistor ratio required to stabilize the DC Operating point.
When the voltage bias and Vt is improperly matched, you may end up with no gain and one device not in the linear Triode mode. But when done ideally, the total AC voltage gain open loop might be as you indicated or it might be gm3* (ro3//ro4//ro6) below the effects of Cx.
However the sensitivity to every component tolerance of each parameter ( Vt, gm, ro, and Vgs bias) will degrade your theoretical voltage gain due to the high derivative slope of d(gm)/d(Vgs-Vg) with the supply Vdd, Vss (+/-5V), Vbias.
You can compute yourself and/or simulate these sensitivity results in Falstad with sliders for every FET and supply parameter . Have fun self biasing it with mismatched parameters. Add your own Miller capacitance.
However a discrete “CMOS inverter” only has 2 FETs like M3,M4 from a single supply then in linear mode, is self biased like an Op Amp with External Rf/Rin and AC coupled or DC coupled with a bipolar supply (unless B buffered type, then 3 stages of gm. ). Then the gm(beta), Vt=+/-1.5 so the supply quiescent current is dependent on these values. This worked famously in the old days with CD4000B series CMOS over a wide supply range as a high gain somewhat linear amplifier.