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I’m trying to implement a circuit by using logic gates where the output is ON only one of the three inputs is available.

Below I wrote down the corresponding truth table and the Karnaugh map for the inputs A, B and C:

enter image description here

Now in this Karnaugh map there is no grouping possible. How can we proceed to form a logic from this point?

Edit:

Here is what I came up with if not wrong:

enter image description here

But this circuit requires 6 AND gates and 2 OR gates.

Is this the limit for simplification? Can this be simplified more?

Edit 2:

Logisim simulation:

enter image description here

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  • \$\begingroup\$ Grouping just lets you simplify the expression. If you can't group then no simplification is possible and you write out the expression as is. \$\endgroup\$
    – DKNguyen
    Jun 16 '19 at 17:15
  • \$\begingroup\$ But what is the expression for a cell here? The circled cells I mean. \$\endgroup\$
    – user1999
    Jun 16 '19 at 17:16
  • \$\begingroup\$ Think about how you would write it out if you had groupings. It's no different. Just that without groupings there are no inputs that dissappear from the term because no simplification. It's actually simpler than with groupings but you're just not used to seeing it that way. \$\endgroup\$
    – DKNguyen
    Jun 16 '19 at 17:17
  • \$\begingroup\$ If I knew or figured out I wouldnt ask the question; this is the exact point Im stuck at.. \$\endgroup\$
    – user1999
    Jun 16 '19 at 17:20
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    \$\begingroup\$ what would you have done if there was a 1 in both cells in the first column? \$\endgroup\$
    – jsotola
    Jun 16 '19 at 17:23
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There is a way to simplify further if you're allowed to use other logic gates than OR and AND. "Diagonal" ones like in the first 4 cells indicate, that some XOR logic gates can be applied. Since KV-Diagrams are toruses the diagram can be rewiritten as follows:

┌──────┬────┬────┬────┬────┐
│ A/BC │ 01 │ 00 │ 10 │ 11 │
├──────┼────┼────┼────┼────┤
│    0 │  0 │  1 │  0 │  0 │
│    1 │  1 │  0 │  1 │  0 │
└──────┴────┴────┴────┴────┘

This reveleals another diagnonal structure, so we can begin to group them together. The first and the second colums are 1, when A and C are equal. This means a XNOR connection: $$\bar{ (A \oplus C) }\land\bar{B}$$ Same goes for the second and third row but with A and B: $$\bar{ (A \oplus B) } \land\bar{C}$$ So the whole expressions boils down to: $$(\bar{ (A \oplus C) } \land\bar{B}) \lor (\bar{ (A \oplus B) }\land\bar{C})$$

Two XNOR gates, Two AND gates and one OR gate.

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  • \$\begingroup\$ Of course, whether using XOR/XNOR gates will actually "simplify" the design depends on how you define "simple". If the OP is just counting the gate symbols on a paper schematic then I agree that you have a better solution. But, just for completeness, if a person is counting transistors in a CMOS VLSI implementation then the XOR/XNOR may not really be any smaller. \$\endgroup\$ Jun 16 '19 at 19:59
  • \$\begingroup\$ Please see my Edit 2. I tried to simulate both ways in logisim. But yours with XNOR gates didn't work as expected. I don't know why.. \$\endgroup\$
    – user1999
    Jun 17 '19 at 10:14
  • \$\begingroup\$ @user1999 You should be aware that there are two "standard" definitions for the behavior of an XOR gate with more than 2 inputs. The IEEE defines XOR as "one and only one" input is high, but other people define XOR to be the same as odd parity. To avoid this issue you can create your circuit using only 2-input XOR gates...that behavior is well defined and consistent. \$\endgroup\$ Jun 17 '19 at 11:45
  • \$\begingroup\$ Yes I tried this with another simulator and it worked. \$\endgroup\$
    – user1999
    Jun 17 '19 at 17:20

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