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I want to design a counter which doesn't increments value every rising clock pulse(assuming positive edge triggered). Say I have a FSM which has 4 states . Only after traversing of the 4 states , I want to increment my counter value . How this can be done ?

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    \$\begingroup\$ Have another counter that counts the 4 clock pulses, and only increment the first counter when the second counter is 3 (or 0 or 1 or 2, your choice). \$\endgroup\$ Commented Jun 17, 2019 at 4:51
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    \$\begingroup\$ You make a counter with an 'enable' input and control the enable from your primary FSM. \$\endgroup\$
    – Oldfart
    Commented Jun 17, 2019 at 4:58
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    \$\begingroup\$ Make a counter with 2 more bits than you want your counter to have, then leave the two lowest order bits out of your output. \$\endgroup\$
    – The Photon
    Commented Jun 17, 2019 at 5:52
  • \$\begingroup\$ A literal reading of your questiosn suggests needing a second FSM that tracks visited states and when all have been visited then causes or allows the counter to increment. \$\endgroup\$ Commented Jun 17, 2019 at 6:10

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The simplest solution would be to use a 2-stage flip-flop-based divide-by-4 circuit between your input clock and the clock input of the counter. Essentially, you would be dividing the clock by 4 before feeding the counter.

One disadvantage of this approach is that the propagation delay of the 2 flip-flops will add up to the transition delay of your counter. You can think of it as two cascaded state machines. If that's acceptable, you're fine.

It you need the output of the counter to change as fast as possible right after the original clock source transition, then you need a single synchronous state machine to take care of the whole thing. In this case you will need 4 times more states then what you would need for a simple counter that changes output at each clock. If you're adventurous, you can design the state machine from scratch using state diagrams and Karnaugh maps, or you could find a binary counter and discard the least significant two bits as @ThePhoton suggested.

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