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I am following the tutorial to turn on the LED on the embedded vision development kit found in:

C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v

and when translating the design I get the following error:

icky debug image with details cutoff

I can't figure out what I did wrong. Is this even an error?

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    \$\begingroup\$ Three things, can you copy and paste what the compiler spat out? Pictures don't help with debugging and you haven't displayed all of the information from the compiler, there's more errors than what we can see in the picture. Secondly, can you upload the code? I only have Lattice files on my work computer so I don't have access to that Verilog code. Lastly, are you absolutely certain you set up the device correctly? A bunch of your errors say that you should refer to the datasheet. \$\endgroup\$
    – user103380
    Commented Jun 17, 2019 at 22:31
  • \$\begingroup\$ Start over and check off every step. ( starting page 6 ) latticesemi.com/~/media/LatticeSemi/Documents/Tutorials/LZ/… you missed a step somewhere \$\endgroup\$ Commented Jun 18, 2019 at 4:42
  • \$\begingroup\$ Page 9 says "For this tutorial a logical preference file named pin_assignments.lpf is provided and contains all the pin assignments needed to program this design project onto the LatticeECP3 FPGA. All changes that you make to logical constraints will be saved in this file until you create a new logical preference file or add another existing one." But this pin_assignment.lpf doesn't seem to be compatible with my board (LFE5UM-85F-8BG756I). Is there a way to generate pin_assignment.lpf ? \$\endgroup\$ Commented Jun 18, 2019 at 18:47

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Check the "File List" tab in the left window. You will find a list of all files included/used for your project. Look for the pin_assignments.lpf file (which is listed under the constraint files). There you can open the file and modify it manually. Alternatively you can use the spreedview tool you already opened to modify it. You have to assign the design ios to the correct PADs. "What" is the correct connections depends on the used board. You mention "LFE5UM-85F-8BG756I" as your chip which indicates that you are mostlikely not using the "default" ECP5 eval board (LFE5UM-85F-PB-EVN). But there is a file similar to http://www.latticesemi.com/view_document?document_id=52479 (corresponding doc for the mentioned eval board) for every lattice semi eval board which provides the needed information AFAIK.

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