Sawtooth signal

Question

I'm trying to create a sawtooth signal using low cost pasive and active components. This will allow me to compare it to an analog signal to output a PWM signal.

My sawtooth signal have to be at least 21kHz and I rely on this scheme:

showed in this youtube video : https://www.youtube.com/watch?v=2a1I1X3RV0g

My power supply for the circuit is 8.2V and the amplitude of the signal has to e the biggest possible. The problem is that I can't simulate on Simetrix a "pretty" sawtooth wave at 21kHz (see picture below)

And my second problem is that I have to connect a follower so i can put my sawtooth signal in a comparator.

Do you have any idea if those problem come from the simulation or it's just impossible to do that ? Or do you have any other circuit to create that wave ?

Thank you.

Answer 1

Instead of generating a sawtooth wave. Why not just generate some wave and let a op-amp figure out the duty cycle?

So allow me to show you another circuit that I think is slightly easier to construct.

Link to simulation

To the left there's just a simple oscillator that gives you a relatively clean sine wave. That is added together with a feedback loop. The feedback loop is trying to make the average of the PWM equal to the input.

For an input of 1 volt the outputs is a PWM with a duty cycle of 20%. 2 volts gives you 40% and etc. Due to the shape of a sine wave, the bottom and top is relatively flat, this means that if the input is near 0.1 volt or around 4.9 volt the output starts getting very dependent on the amplification of the transistor. A solution to this would be to cascade with yet another transistor and change the feedback loop slightly, set up a darlington configuration, add two transistors and keep the feedback. Or just go with any other answer that doesn't depend on a sinewave as the wave to compare against.

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Update due to comment:

The name for this particular circuit? "PWM generator"? I've come up with this one myself. So I'll just call it what it is. A PWM generator. The oscillator used is one of hundreds of variants of a Colpitts oscillator with the twist that you let the output be its gate instead of its drain or source. To my understanding, any oscillator that uses two capacitors, one inductor that define the oscillation frequency and one or more transistors to make it oscillate is a Colpitts oscillator.

I think it will work with any logic level NMOS, as you can see in the simulation it is oscillating between ~3 and ~0 volts, that is because the threshold voltage of the NMOS is 1.5V. One NMOS that I've used for this setup is the AO3402 which is a logic level NMOS. The oscillation is almost identical to the image above.

My design was supposed to be as easy to modify as possible, with that said, it is very possible to make small tweaks so the output of the op-amp never has to go below 0V. Or for the output to be more "digital", as in generating a better square wave. Now, why didn't I show THIS circuit instead? Because then it's not as easy to modify, it's more difficult to understand, and you'll get angry because it might not work with your particular setup. Your setup which I have 0 clue about. I'm quite certain that you'll have to modify my circuit to make it fit your needs. Hence I showed you the basics of making it work.

Answer 2

I see your problems. Do I need a diagram to explain?

Your random level and frequency shift are due to a PNP Emitter follower not shown in your schematic which causes Vbc forward conduction from the negative voltage on C1. Because it (Q4 not shown) see almost -0.6V it is on the verge of conduction results in the consequences of your waveform.

Clamping that with a Schottky diode would compromise your amplitude.

So what do you do?

• don't add a series R to invisible Q4 because Q1-c is a current source and that leakage will cause overshoot on the return stroke if you care(?). So it must be equal to or greater than the Early effect leakage resistance of Q1 for a pristine sawtooth. (which I won't bother to explain may be around >=100k) But maybe you don't need to clamp overshoot.

So change that invisible Q4 (and don't hide things from us again) to an Nch Enh.FET common source or a P ch Common Source. That will give you >5Vpp signal and the level shift will be determined by the Vgs(th) which unfortunately is very loose so that is not a great solution. ( there are many better solutions, but I tried to explain how to fix your signal integrity, not meet some undefined voltage and risetime specs.) Pch Vgs(th)=4V should give you 0.5 to 6V negative ramp sawtooth.

But you really ought to reconsider re-inventing the wheel, define your specs ( which all good designers do in their head or on paper) and then realize what is better, make or buy!! I do not see in either of your two similar questions any specs other than as big as possible at least 21kHz ( a nice VLF Navy channel)

My solution using transistors with fast recovery time.

My Mods

• I now get a full rail to rail sawtooth to 8.2V by changing the resistor ratio to 10k:100K for the trigger to raise the trigger voltage.
• I changed R bias Current source to a simple CC source with 2 diodes.
• With lower bias currents I now had to reduce C to get 100kHz , but this is adjustable with the CC emitter bias resistor such that Ic= 0.35V/Re( 10k)
• The voltage drop is not 0.7 but 0.35V, because I am only using Ic=35uA whereas you were using 4.5V or so.

Your problem

• with no resistor on Q4-b and CB becoming forward biased. ( which I had to imagine that you had, even if it was obvious to some)