# Understanding this power supply design

I'm doing some kind of reverse engineering to this very old power supply design. I'm having hard time trying to understand it all. I'm asking for some hints that help me read this schematic. From this circuit, you should know:

1 - The line to line voltage is 480 VAC.

2 - The input to the LM317 is +27 V as marked. Don't understand how +27V is generated in that arrangement.

3- The reference is not 0V for the bridge rectifier. It's -13V coming from the regulator.

4- The output of the LM317 (+13.25V) feeds another control circuit that I'm not showing.

5- When the coil is activated, it shut downs the main power.

What I really want to understand is how the +27V is generated, and how the FET is turned on. My guess is that when the control circuit gives the signal to the SCR, it activates the coil, but don't understand how. You can see this design is strongly dependent on the zener diodes. There are 4 zener, 43V, 10V, 12V, and 13V. How would you improve this circuit?

EDIT: The three diodes in series below the coil are TVS diodes. Each one is 300V, so the total reverse breakdown voltage is 900V.

• The reference is -13V with respect to what voltage? – Voltage Spike Jun 18 '19 at 20:39
• I guess GND, which is right of C3 and C4? – Huisman Jun 18 '19 at 20:40
• What triggers thyristor TR1? – Huisman Jun 18 '19 at 20:40
• The zero voltage point is the cathode of the 13V zener, the mid point of the two output capacitors. Really don't understand the complexity of this circuit. Didn't know you could create a negative reference like this – user115094 Jun 18 '19 at 20:41
• TR1 is activated by a big control circuit I'm not showing. The whole device is an earth leakage protector, so there's a current transformer which is being monitored. – user115094 Jun 18 '19 at 20:43

The circuit is easier to understand if it is redrawn so that voltages increase strictly from bottom to top.

I've drawn the rectifier as a floating voltage source for simplicity.

Since ground is defined as the point between the two output capacitors, then D15 establishes the most negative voltage as -13V.

D14 then puts the ADJ pin of the regulator at +12V, which means that the regulator output is 12 + 1.25 = 13.25V.

D8 regulates the gate of Q1 at 43V above the negative rail, for an absolute voltage of +30V relative to ground. Note that Q1 is wired as a current limiter.

Since you're measuring the input of the regulator at +27V, then there's a difference of 3V between that point and the gate of Q1. Most of this is the threshold voltage of Q1, but there will also be a voltage drop across R2 + R3 that depends on the load current.

D7 limits that voltage to 10V at most, which means that the maximum current that can flow through R2 + R3 is about $$\\frac{7\text{ V}}{515\Omega} = 13.6\text{ mA}\$$ — at which point, the input voltage to the regulator will have dropped to about 20 V. Presumably, this range of current is not enough to activate the coil.

If TR1 is triggered, then the current is limited only by R2, which means that about 1.37 A will flow through the coil, at least until the power source is cut off.

• Thank you. I´m definitely more clear with your redrawn circuit. My only question now is, if the three TVS diodes are between the drain and -13V point, does this mean the TVS diodes are protecting the FET against transients, but not the coil? – user115094 Jun 20 '19 at 23:03
• That's right. It's the coil that generates the transients (mostly), from the collapse of its stored energy. – Dave Tweed Jun 20 '19 at 23:10
• I assume they have used three TVS diodes to protect against higher surge current. But, isn't there a way to reduce the number of diodes? That design is kind of old, so maybe nowadays there are better solutions. – user115094 Jun 25 '19 at 15:38

Power line transient is also a major fuse blower with Z1 OVP protection.

The 3 phase bridge produces 6f frequency ripple which is used to drive the FET as a BUCK regulator with Zeners to limit Gate drive, LDO input max and forward current to power tthe load.

Given the LDO operates at 1.25 between Vout and Vadj, with a short circuit between these the output is 1.25V above the Vadj Zener voltage of 12V. The LDO regulates the output but must charge up the output caps which must not be excessive as the energy to charge these up at 13.2V is only 13.2/600V+ = 2% of what the drop down circuit must dissipate getting started. So the SCR is I used as a soft start latch to bypass the series R which limits the start current.

But if there are any power interruptions and the SCR is not able to shut off in time for the resurge of power, the fuse will blow.,

If this is the case then an undervoltage lockout UVLO must be designed to prevent this occurrence with a retry on UV ok and the SCR unlatched. If you cannot come up with an elegant solution maybe a relay will perform better than can be unlatched easily with UVLO status and restart the soft start., You needs to compute the excess power dissipation weakpoint and choose the proper threshold for UVLO. In PC PSU’s they have an analog timer to prevent the PSU from being power cycled abruptly. Why? Because they often use NTC ICL ‘s to create an InRush Current Limit. ICL’s are cheap for startup but take a second to cool down., PTC polyfuses are the opposite and protect thermal damage by self heating to 135’C while increasing resistance orders of magnitude as required.

These may suggest alternative solutions to prevent breaker or fuse blowing from unknown causes.

Summary.

‘Since efficiency is low, output power might only be 2% of input surge power if not correctly started with soft start circuit or ICL’s and UVLO.

Solutions suggested range from UVLO, Relays instead of SCR, ICL’s and PTC’s.

• Comments are not for extended discussion; this conversation has been moved to chat. Any conclusions reached should be edited back into the question and/or any answer(s). – Dave Tweed Jun 19 '19 at 19:13

I really want to understand is how the +27V is generated...

R1 and D8 are a simple zener regulator to 43v. Then D7 subtracts another 10v off of that for about 33V. 20% isn't out of the realm of tolerances for zeners. I'm betting that the 27v varies depending on what is going on. It's just a pre-regulator to the LM317.

and how the FET is turned on

D1-D6 full wave rectify the AC into DC, then R1, D8 and D7 drop the voltage down to about 10V on the Q1 gate to source. This will turn on the FET.

how is the coil activated so it shut downs the power and the FET will turn off?

The FET is on at power up but TR1 is off. So it would appear that the coil can't turn on with the added R3 in the way. When TR1 is turned on it bypasses R3 and allows the coil to activate. D9-D12 are all protection diodes for Q1 and TR1.

In this circuit, Q1 will only turn off when the power coming through L1-L3 is removed.

• So the FET is always turned on while power is applied, but how is the coil activated so it shut downs the power and the FET will turn off? – user115094 Jun 18 '19 at 20:52
• 43V with respect to what voltage? not to GND – Huisman Jun 18 '19 at 20:58
• @Huisman Everything eventually refers back to the source. 43v is directly across D8. That's the main pre-regulator chopping down the 480VAC. If one were to reference it to the GND net label, then it would be different, you are correct. – Aaron Jun 18 '19 at 21:04
• +27V is with respect to GND. The values 43V and 33V you mention, are not with respect to GND – Huisman Jun 18 '19 at 21:11
• You can't assume that there's current flowing through D7, or that the voltage across it is always 10V. – Dave Tweed Jun 23 '19 at 10:53