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Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals.

IBUFDS #(.DIFF_TERM("FALSE"), .IOSTANDARD("DEFAULT"), .DQS_BIAS("FALSE"), .CAPACITANCE("DONT_CARE"), .IFD_DELAY_VALUE("AUTO"), .IBUF_LOW_PWR("TRUE"), .IBUF_DELAY_VALUE(0)) sys_clock_ibufds (
    .IB(sys_clock_n),
    .I(sys_clock_p),
    .O(sys_clock)
);

According to the "AN307 Intel FPGA Design flow for Xilinx Users" Document, Table 38, The Intel equivalents is just simply using wire/signal and IO Assignment. Can anyone give me the example how to do it?

However, I also found this link : https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd01062009_916.html which suggest using the I/O Buffer (ALTIOBUF) IP Core. Which option should i go for the best?

Thanks in advance.

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For differential inputs it is sufficient to create a mapping for the port to the positive pin of the pair, specifying a differential I/O standard. This automatically creates a second mapping for the negative pin, and the I/O buffer IP is inferred from that during place&route by pattern matching.

You can make that explicit if you like, but the result is identical.

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