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In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There is possibility that the 1st clock edge coming to launch flop having positive jitter and clock edge coming to capture flop having negative jitter(worst case possible) So in this we should take twice the value of jitter in calculation right?

And for hold calculation, since same edge is being used, there won't any effect of jitter right? Please correct me if I am wrong.

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  • \$\begingroup\$ Does edge-triggered, versus level-triggered, matter? \$\endgroup\$ – analogsystemsrf Jun 20 at 3:34
  • \$\begingroup\$ As long as both FF have matched thresholds and t.prop, for a finite rise time, it won’t matter. But S/H cap must be NPO or film as the others have hysteresis. But more important is the Nyquist image signal suppression =>Fs/2and group delay near breakpoint of signal fMax \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 20 at 17:59
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Jitter is measured with respect to some reference clock edge. If you have a situation with only two clock edges, and you allow for either positive or negative jitter, then it doesn't matter which of the two edges "has jitter" with respect to the other edge.

If the jitter is specified with respect to some third clock then it would make sense to assume that one flip-flop sees positive jitter and the other sees negative jitter. In that case, doubling the maximum jitter makes sense.

The important difference between these two cases is how the jitter of the two clocks is specified, either with respect to each other or with respect to some third clock source.

Regarding the hold situation, the data input for some flip-flop is coming from some other flip-flop. Clock jitter will affect the arrival time of that data so clock jitter between the two flip-flops is still relevant.

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