I'm trying to derive an accurate formula for the output of an error amplifier in the class D amplifier I'm simulating. Most literature on the error amplifier/integrator in class D amplifiers glosses over the technical details and and some even contradict eachother in how it works.

In the previous question I asked here, we found the transfer function of an ideal summing integrator:

$$ V_{\text{OUT}} = \frac{V_{\text{FB}}}{\omega R_{\text{FB}} C} + \frac{V_{\text{IN}}}{\omega R_{\text{IN}} C}$$

I tried applying this to my simulation but come up short. My understanding, based on the simulation is that the circuit integerator acts as a filter to the sum of the two inputs with a -3dB frequency at roughly 41kHz. I'll attach pictures of the simulated results below at 1kHz but i increased frequency until i got 3dB attenuation and it was around 41kHz.

My question is, how can the equation above be accurate when it depends on frequency and a lower frequency means a higher gain? At 1kHz using the values of the simulation below at t = π/2:

$$ V_{\text{OUT}} = \frac{-1.6}{2 \times \pi \times 1kHz \times 5.9k \times 220pF} + \frac{0.95}{2 \times \pi \times 1kHz \times 3.6k \times 220pF}$$

$$= -5.28V$$

This does not match the plotted value of roughly -3.7V. This calculation becomes more wrong as the frequency changes. In the time domain, the integral equation also does not make sense with huge numbers generated by the time constant 1/RC. How can I mathematically express the output of the error amplifier in the below circuit better?

Circuit is a unipolar PWM switching class D amplifier at 500kHz.

enter image description here

To be clear: Green is input, Red is feedback signal and contains 1MHz triangle wave ripple. I assume this ripple is caused by the 1/RC relationship on the differential amplifier (U1) where the square wave inputs are attenuated and integrated. And blue is the output of the error amplifier/integrator (U2).

enter image description here

Edit: From the advice of Sunnyskyguy EE75, i'll attempt to construct a transfer function based on the loop shown below.

enter image description here

G1 is the preamplifier gain that is not included in the simulation.

H1 is the differential amplifier gain:

$$H_1 = -\frac{R_2}{R_1}V_{\text{OUT}}$$

Vout is a peak to peak sine wave of roughly 12V so this makes sense with resistors R2 = 1k, R1=6.8k looking at the waveform.

G_PWM is simply Vint as a ratio of the carrier signal which is a triangle wave 500kHz +/-4.2V:

$$G_{\text{PWM}} = \frac{\left \lvert V_{\text{INT}}\right \rvert}{4.2} \times V_{\text{DD}} $$

Gint is still unknown to me.

VN is noise introduced from switching/deatime.

  • \$\begingroup\$ More important is what is your ideal transfer function and impedances for source and load that you want to apply. Feedback will only make it unstable unless you compensate for the loss of phase margin from integration. \$\endgroup\$ Jun 21, 2019 at 4:27
  • \$\begingroup\$ The error correction is greatly dependent on GBW or the feedback gain to reduce the input ERROR for the virtual ground. Then the phase margin of any control system must be designed for stability with design specs. Of course integrators increase gain with lower freq and thus reduces input error but also adds 90 deg lag...which I think was your question. but its an XY question. \$\endgroup\$ Jun 21, 2019 at 5:27
  • \$\begingroup\$ @Sunnyskyguy EE75 Are you saying this simulation is inaccurate and the circuit won't work? What methods of phase margin compensation are you talking about? \$\endgroup\$
    – dos584
    Jun 21, 2019 at 5:28
  • \$\begingroup\$ I did not check your simulation but your design method is in doubt without an overall voltage and impedance transfer function. After this is done then if you need to to do Negative Feedback , we can see if that is possible for the sig BW you want for amplitude and phase shift flatness. Easy for a DC voltage SMPS to have 20kHz BW but not so easy for 60dB SNR and <<1% distortion at high dynamic power ranges \$\endgroup\$ Jun 21, 2019 at 5:30
  • \$\begingroup\$ @SunnyskyguyEE75 Sorry mate, been a bit busy, I made a small edit with some info on the transfer function, let me know if i'm on the right track. As per your second reply above. I acknowledge that integrators should increase gain with lower frequency, my question was about what compensation is at play because the circuit shows a flat until the -3db frequency of roughly 41kHz from simulation. \$\endgroup\$
    – dos584
    Jun 24, 2019 at 15:20

1 Answer 1


Ignoring the voltage gain of the Half bridge and just making a feedback loop of the filters;

I get a feedback loop with a fixed low gain <1 proportional to the 500kHz carrier with k1 from R ratios and T1,2,3 from RC products.

enter image description here

I did not bother with the equations but rather direct into simulation with a slider for signal frequency.

e.g. above signal levels have input carrier Vc ~ 10Vp and output PWM = 15Vp with analog signal on 2nd stage as "output= ~4*Vc" so a net gain of 0.4 Vc. using 15V PWM supply peak.


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