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So I've got a fairly basic circuit set up for load modulation of an inductively coupled circuit: circuit

A few notes on the above: LC's were designed for 1 MHz but work better at 950 kHz, thus the chosen frequency. C8 is ~2.7 nF, rectifier caps are 10 nF, noise cap (farthest right) is 10 uF. The load is a couple of regulator and oscillator IC's. Diodes are 1n4148's, NMOSFET is 2n7000. I've got a question mark drawn for the gate input since I've basically just measured a reduced amplitude version of my current Vds signal there whereas it should be zero (the output of an LTC6990 when its power is too low to turn on), so that's a bit confusing.

I'm transmitting across a ~30 Vpp sine wave from a Class E amplifier that isn't well tuned but it appears to be sufficient. The problem is essentially this: with the MOSFET removed, my inductive link is excellent (nearly 1:1 waveform shapes and amplitudes transmit across) and all my IC's turn on and do their jobs (regulators, op-amps, and the modulation oscillator work great)... before MOSFET install Yellow channel: Vin on Tx side. Blue channel: output of oscillator on Rx side, which goes to MOSFET gate.

...but with the 2n7000 installed I get an odd "rectification" and significant reduction in amplitude (down to ~1.6 V). You can see this in the waveforms below: issue Yellow channel: Vin on Tx side. Blue channel: Vin on Rx side (or across C8, or Vds, all are the same nodes).

I thought maybe there was self turn-on occurring so I tried some caps between the gate and source (470 pF and then 1.5 nF) but there was no change. The FET does appear to be on most of the time (with the exception of the 200-300 ns where voltage can actually rise across C8), and I'm sure some of this is due to Vgs surpassing Vt when the source side is going negative but the voltage doesn't seem exactly right (datasheet for 2n7000 says Vt can be as high as 3 V but should be more like 0.8 V). The time constant of the Vin rise/fall suggests the ripple tracks more with the transmitted flux than with any kind of RC-induced decay.

I have also pulled the 2n7000 off, replaced it with a new one, and gotten the same behavior; I also tested the one I pulled off with a simple LED test circuit and it still works.

As a note, I have seen a circuit in this configuration (layout and IC selection) work, with slightly different LC's a cap values.

Any thoughts here would be greatly appreciated, feeling like I'm missing something very basic.

Edit:

Forgot to clarify what I was expecting (and how the previous iteration of this circuit worked). The Rx should like something this at the drain node: modulated That shows up back in the Tx due to load modulation, then I filter it and measure the modulation frequency. Ignore the numbers in the simulation, intention is just the basic layout.

Edit #2

Based on Russell and Bruce's suggestions, I attempted to make use of two series FETs in the configuration shown here: dualFET You'll note that I left the 3.3 V oscillation since I can't do anything about that at the moment (working from a PCB and limited components so can't change regulators right now). I did include the series resistances Bruce mentioned (LTSpice doesn't show the coil series R but I did add it).

I now get a clean waveform across the Crx: new Vin This is more than enough to turn on all my regulators and IC's and I see proper supply rails.

However, I'm back to seeing a modified Vin (Vds) at the node where the oscillator output joins the two gates: new Vg I can tell that this isn't the oscillator output because it's the same frequency as the input AC (oscillator isn't configured for that frequency range) and the amplitude is too low (should be GND to V+, which is 3.3V).

For experimentation's sake, I tried two more things: connecting the node between the two source pins to GND (didn't change anything) and also just connecting the LTC output directly to the top of Crx (could see the modulation on the Rx side now but the load change was too minimal to be seen back on the Tx coil).

Next I'll try cutting the trace on the source side and placing a series FET there, as suggested below.

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  • \$\begingroup\$ Why should it work with bipolar voltages? Don’t you want it on the output? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 20 at 23:33
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    \$\begingroup\$ The 2N7000 has a body diode which means it conducts Vds when Vds is negative. If you want to modulate an AC signal you'd need two in series with opposed po;arity (s1 to s2, g1 to g2, d's form the two outputs, gate signal from gates to drains. You need a floating gate drive (gs to ss) . It works. \$\endgroup\$ – Russell McMahon Jun 21 at 1:51
  • \$\begingroup\$ @RussellMcMahon - yeah, I knew that would occur to a certain degree but given the Vt value, I just assumed it would happen for ~1/2 of the negative cycle and nowhere else. This behavior makes it look like it's almost always on. Thanks for the redesign suggestion, though, I'll likely redesign it the way you suggested! \$\endgroup\$ – PoGaMi Jun 21 at 14:14
  • \$\begingroup\$ For anyone that views this later, the "copied" Vds signal at Vg was due to a faulty op-amp output; the VCO was turned off due to the input signal voltage being out of range and so the VCO was instead just amplifying ripple on the power supply line. \$\endgroup\$ – PoGaMi Jun 24 at 17:00
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Your simulation has some problems.

First problem is the FET is wired directly across a voltage source which has zero output impedance, so no matter how well it is turned on it won't affect the voltage.

Second problem is there is no return path for the Gate drive. The entire circuit is floating, so it simply jumps up and down in time with the Gate drive and the FET never turns on.

Third problem is 200us is not nearly enough time for the 10uF output capacitor to fully charge, so even with the other problems fixed you won't see the 'steady state' waveforms.

Your schematic shows the circuit grounded at the load, so I added a ground there. To (roughly) simulate the source impedance I added 250Ω to V1. I also added 100Ω to the Gate drive signal to simulate the output impedance of the LTC6990. The DC output took a long time to stabilize so I reduced C7 to 1uF and changed the simulation time to 1ms. Here are the results:-

enter image description here

Zoomed in to show a few cycles of the last FET 'off' period.

enter image description here

The FET body diode is turning on during each negative half-cycle, flattening the bottoms of the waveform. You can also see a reduced amplitude wave feeding through to the Gate via capacitances inside the FET.

My source impedance choice was just a guess, and doesn't simulate the complex impedances typically found in rf circuits. If the Class E amp and coupling coils were also accurately simulated the waveforms should look closer to what you got in reality.

So much for simulation, now the real problem - you can't use a MOSFET to modulate an AC waveform larger than ~0.6Vpk without distortion because the body diode will conduct during negative half-cycles. To fix this you could put two FETs in series 'back-to-back' with Drains and Gates connected together, then one FET's body diode will always be reverse biased. Also you should provide enough Gate drive voltage to ensure the FETs turn on fully. 3.3V is not enough for a 2N7000.

You might also consider putting the FETs in series with the source instead of in parallel. Then they would disconnect the source when off, which could be more efficient than 'shorting it out'.

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  • \$\begingroup\$ That's a great answer, thank you. As noted above, I knew I'd get conduction for a part of the negative half-cycle but not for as long as it was happening, due to the expected Vt of the FET. Vt in these FETs is ~0.8 - 3.0 V, depending on the series, so are you saying that 3.3 V isn't enough because drain currents will be low or because I'm not overcoming the source voltage for most of the cycle? \$\endgroup\$ – PoGaMi Jun 21 at 14:24
  • \$\begingroup\$ Oh sorry, one more thing: the 10 uF cap is actually a noise cap for the positive-side regulator that comes after, I just wanted to include it in this snip of the design in case there was some major Ceq issue I wasn't noticing. \$\endgroup\$ – PoGaMi Jun 21 at 14:34
  • \$\begingroup\$ 10uF is fine - you just have to remember that it will take a long time (in simulator time) to charge. I only reduced the value to make the simulation go faster. By 'Vt' I assume you mean the Gate threshold voltage. This is the voltage at which the FET just starts to turn on (Id = 1mA max). To achieve lowest on-resistance it needs 10V. The "On-Region Characteristics" graph in the datasheet is for a FET with typical threshold voltage - you should assume it could be significantly worse. \$\endgroup\$ – Bruce Abbott Jun 21 at 23:54
  • \$\begingroup\$ So there were some connection issues on the board but the resolution still turned out to be placing those two FETs source-to-source. Thanks for the advice! \$\endgroup\$ – PoGaMi Jun 24 at 3:38

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