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If I have a 1 Gb memory with EDAC for single bit correction for a critical application, what could cause a double bit error in this memory? Provided that the queues never get out of sync which causes writes to memory to become corrupted. What other phenomenon (hardware/software related) do I have to consider to take into account for the probability of a double bit error to occur?

It's for an aircraft application, so thats why I included hardware, where we can have single event upset. I am just looking for a probability number I could come up with to justify using EDAC with SECDED.

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  • \$\begingroup\$ Failure analysis for aerospace applications is a non-trivial problem and you have asked an extremely broad question. This is not the kind of thing you research in an internet forum. Do you know the single-event upset cross-section of your memory? Do you have an estimate of the high-energy particle spectrum for the application? \$\endgroup\$ Commented Jun 21, 2019 at 20:59
  • \$\begingroup\$ I gave a vague answer to a vague question, but I did answer one of the questions. ...what could cause a double bit error in this memory? high energy particles can flip bits. Besides what Elliot said, you also need to know the probability of failure (double bit error) you can tolerate. If there is any chance of a single bit error, there will be a smaller probability of a double bit error, no matter what mitigations are in place. \$\endgroup\$
    – Mattman944
    Commented Jun 21, 2019 at 22:18
  • \$\begingroup\$ @ElliotAlderson I know its an extremely broad question, since I am fairly new to this particular concept I don't know what question I should be asking. The question you asked helps a lot. I have a broad number from a study that gave failure rate for 10E-5 error/hour for the cross section of area for 1GB of memory with same cross-section as what I am planning on using. \$\endgroup\$
    – Huntkil
    Commented Jun 21, 2019 at 22:57

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Hardware: Certain high-energy radiation events can cause a shower of particles that affect multiple nearby bit cells. This is rare; how rare depends on the memory technology and the environment.

Software: Rowhammer-style attacks can sometimes flip multiple bits at the same time or within a short time interval.

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  • \$\begingroup\$ Crosstalk is the cause of these events \$\endgroup\$ Commented Jun 22, 2019 at 2:13
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    \$\begingroup\$ Two bit errors don't need to be nearly simultaneous. If a single bit error hasn't been fixed and another occurs at the same address 5 minutes later, it is still a serious uncorrectable error (assuming SECDED). \$\endgroup\$
    – Mattman944
    Commented Jun 22, 2019 at 7:31
  • \$\begingroup\$ @Mattman944 good point. Rad-tolerant computers often try to mitigate this by having a background routine that regularly "scrubs" the memory, reading every address (or at least every address that's allocated) so that the EDAC hardware has a chance to catch and correct single errors. With modern RAM speeds this can usually be done every couple of seconds without significantly impacting CPU / bus utilization. \$\endgroup\$ Commented Jun 22, 2019 at 17:06

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