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I've seen conflicting descriptions and conflicting implementations of D Flip Flops, when it comes to how the Flip Flop behaves when its input value changes at the same time the clock rises.

Implementation #1:

[CLK] [IN] [OUT]
 0     1    0
 1     0    0

Implementation #2:

[CLK] [IN] [OUT]
 0     1    0
 1     0    1

In other words, Implementation #2 will always store the value that [IN] had during the first half of the clock cycle, but Implementation #1 will pick up the value of [IN] on clock rise.

Which implementation is correct, or standard?

If I buy myself the most widespread Flip Flop model in a store, how is it likely to behave?

UPDATE:

The following implementation (in Digital) behaves like Implementation #2.

enter image description here

However, it behaves differently from how Digital's built-in D-Flip-Flop component behaves (it behaves according to Implementation #1).

Would you say that either implementation is correct or better?

Which implementation am I more likely to find in actual hardware?

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  • \$\begingroup\$ If these are supposed to be truth tables, they are poor. Each line should be stand-alone and not depend on the previous state. The clock column should indicate an edge. \$\endgroup\$ – Mattman944 Jun 22 at 22:33
  • \$\begingroup\$ @Mattman944 then please feel free to consider them NOT truth tables... \$\endgroup\$ – obe Jun 22 at 22:34
  • \$\begingroup\$ Real ones are usually built as a pair of latches and an inverter, but the latches are generally transmission gate based, and the transistor geometry is very carefully tweaked to make the timing do something reasonable (This is how some parts have zero setup time). \$\endgroup\$ – Dan Mills Jun 22 at 22:57
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The most common behavior for a flip-flop is to store the value of its data input at the instant that the clock rises. In reality, the logic value at the data input must be stable for a short period of time before the clock edge (the setup time) and must remain stable for a short period of time after the clock edge (the hold time). Conceptually, the flip-flop only cares about the data input value at the instant that the clock rises.

Having said that, it is also possible to build flip-flops that change state at the falling edge of the clock rather than the rising edge.

Also, some people use the word "flip-flop" to refer to what I prefer to call a level-sensitive latch. Since your question talked about when "the clock rises" I am assuming that you are asking about an edge-sensitive flip-flop.

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  • \$\begingroup\$ Thank you for your answer. Could you please have a look at the update in the question? \$\endgroup\$ – obe Jun 22 at 22:39
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    \$\begingroup\$ The schematic looks correct for a flip-flop but the two tables you provide (for implementation #1 and #2) are not valid. In both cases you appear to change the data input and the clock input at the same time, and that is not legal. The behavior of a flip-flop is usually undefined in this case...it could do anything. That's true both for simulations and in real life. Make sure that the D input does not change at the same time that the clock is rising. \$\endgroup\$ – Elliot Alderson Jun 22 at 22:46
  • \$\begingroup\$ at the instant that the clock rises .... it could also be at the falling edge .... your answer should have a different wording .... something like at the instant of the trigger transition of the clock \$\endgroup\$ – jsotola Jun 23 at 1:36
  • \$\begingroup\$ I didn't want to begin with language that introduced new concepts before the OP was clear about how rising-edge flip-flops work. That's why I was careful to say "the most common behavior". Then, in my second paragraph, I generalized the answer to falling-edge flip-flops. My goal was to provide scaffolding from what the OP did understand to what they needed to learn. \$\endgroup\$ – Elliot Alderson Jun 23 at 12:50
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Firstly there are D flipflops available that trigger on (Depending on the part) the rising or falling edge.

Secondly D changing too close to the triggering clock edge (which ever one it may be) tends to cause the mess known as metastability where the output can hang in an undefined state for an undefined length of time and can even (depending on what the following device thinks logic thresholds are) switch states a few times. The datasheet has values for setup and hold times, violate them at your peril, because 1 or 0 are NOT the only possible outcomes!

This is a major pain when crossing clock domains in things like FPGAs as the fixes are basically to cascade a few flipflops on the output clock domain and do statistics on how often it still bites you.

So the answer to your question, is either, both, neither depending on how unlucky you get, don't do that!

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