I'm trying to construct an 8-Bit Program Counter, in Logisim. It currently has functions LOAD, which makes the 8-Bit input (A0-A7) appear at the output (S0-S7) on the clock pulse:

Loading 1 as input: LOAD 1

1 successfully loaded/stored: LOAD 2

When LOAD is high, A0-A7 is run through the full adder, which technically is used - it just adds 0, so therefore doesn't affect the output.

Now I'm trying to implement an INC (increment) also, which when high will basically just add 1, but take the current register value as the input, rather than A0-A7. Here is the logic flowing in the simulation, which is exactly what I want (I've circled the value going into the register, which is 2 - perfect): INC

However, now when I try to store this value in the register by pulsing the clock - I get an 'oscillation detected' error in Logisim: ERROR

This is the first time I've tried to build this, so is there something intrinsically wrong with my implementation, or am I missing something small which should make it perform as expected?

  • \$\begingroup\$ Can you put some labels on your inputs/outputs for the full adder and mux? I suspect that you are getting a circular dependency in that the adder is trying to add 1 to the output of the register, which is presenting the adder with new inputs via the mux, but it's hard to tell without labels! \$\endgroup\$
    – srl100
    Jun 24, 2019 at 16:20
  • \$\begingroup\$ Do you have any documentation on that "register"? I can only see some kind of problem there if a) that's a transparent register (outputs follow inputs as long as the "clock" is high) or b) the simulator cannot calculate that loop even tough it's not an invalid real world situation. \$\endgroup\$
    – RaphaelP
    Jun 24, 2019 at 16:37
  • \$\begingroup\$ @srl100 Of course, slipped my mind entirely. Now updated! \$\endgroup\$ Jun 24, 2019 at 16:46
  • \$\begingroup\$ @RaphaelP An abstraction of the register would be: Output = Input when LOAD is high AND CLK is pulsed. Output is stored/persistent in all other states, regardless of inputs. \$\endgroup\$ Jun 24, 2019 at 16:50
  • \$\begingroup\$ Does this register have any attributes/properties that change the way it behaves? \$\endgroup\$
    – RaphaelP
    Jun 24, 2019 at 16:56

1 Answer 1


Your register is propagating it's output based on the "clock" level and not it's transition (aka transparent register), which is creating an unstable loop. For that circuit to work, you'd have to:

  • Change that part to a register that changes it's outputs only at the clock's transition from low to high.


  • Add a second register after the first that's clocked by the inverse of the first one's clock. By doing so, your circuit still takes 1 clock to output the changes to the bus, but it does so in two steps, preventing the register's changing output from affecting it's own input.

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