I am trying to build a Butterworth bandpass from 130MHz to 140MHz (approx.). As I have already worked with microstrip lines of transmision, I wanted to give coplanar waveguides a try, as in the future I plan to work with higher frequencies (>10GHz) and I have been told that in those cases they behave more efficiently.

My coplanar waveguide is a feed line of 2mm spaced 0.49mm to ground. The board will be 1.6mm thick and use FR4 dielectric (relative permitivity of around 4.6). The expected impedance is 50 ohms.

As of now, I have finished designing my PCB, but I have two main doubts:


  1. Can those soft curves on the upper ground plane, that KiCad adds automatically around the pads of the capacitors, affect the behavior of the waveguide?

  2. Have I added too many vias around the signal line? And are there enough vias all over the rest of the board? I am a bit lost about vias.

Thank you in advance!

Edit 1: Thank you for the comments and answer, I have edited my design to this new PCB:

PCB 2.0

Edit 2: Thank you again for the information. This is the latest design. As I read here, it is necessary to add lots of small vias nexT to the main trace very close together. However, there is very little information about this on the internet, I cannot find any exact number/density of vias, their size or how far from the trace should thEy be.

PCB 3.0

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    \$\begingroup\$ you're throwing away one of the benefits of coplanar, C2L1 and C4L2 should not be on stubs that break the ground continuity to the side, they should straddle between the line and the adjacent ground. If those vias are going to a ground plane on the back of the board, then you don't have coplanar, you have 'coplanar above ground', which is just microstrip really with managed encroachment of side grounds. \$\endgroup\$
    – Neil_UK
    Jun 24, 2019 at 20:25
  • \$\begingroup\$ @Neil_UK Thank you for your apportation! Then, would you suggest using less vias? or keeping them farther away from the signal line? \$\endgroup\$ Jun 24, 2019 at 20:38
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    \$\begingroup\$ @user3141592 vias every 1/20 th wavelength were fine \$\endgroup\$ Jun 25, 2019 at 0:19
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    \$\begingroup\$ not critical here for 135MHz but then for 10 GHz you would use smaller microvias and Telfon \$\endgroup\$ Jun 25, 2019 at 0:34
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    \$\begingroup\$ The inductance comes from the return path from the L ground to the C ground. Probably doesn't matter at low frequency, but may be important at high frequency. \$\endgroup\$ Jun 26, 2019 at 1:33

2 Answers 2


Can those soft curves on the upper ground plane that KiCad adds automatically around the pads of the capacitors affect the behavior of the waveguide?

Above 10 GHz, they might.

In Altium I can add a "keep out" to prevent these features from being produced. You should be able to do something similar in KiCad.

Have I added too many viases around the signal line? And are there enought viases all over the rest of the board? I am a bit lost about viases

You can't really have too many vias. If you are not trying to save fractions of pennies, I wouldn't worry about too many vias.

The issue I would worry about (for a 10 GHz design, not for 100 MHz) is that where you tee your line to connect to the shunting LC components, you break the coplanar geometry. Without more analysis I couldn't say what frequency that will start to affect your performance, but at some point it will.

Thank you for the comments and answer, I have edited my design to this new PCB:

Ideally, don't make stubs to connect the L and C. Just put their pads right on the main signal trace. Allow the ground to fill in under the part so you maintain your 0.49 mm from the trace to ground.

Spread out C1, C3, and C5 if you have to to make things fit.

Doesn't particularly matter if you have L on one side of the trace and C on the other (assuming you can fit two pads on the trace without changing the trace width), or both on the same side of the trace.

  • \$\begingroup\$ Thnak you for your answer. Then, would you suggest placing the capacitors and the inductors in a + shape? (being the - is the signal line) \$\endgroup\$ Jun 24, 2019 at 20:39

With FR4 50 Ohms tracks just under 2:1 track width:height above ground plane so 2mm track means about 1m dielectric thickness if DK=4.4

Adding Coplanar grounds with 0.49 mm gap increases height so w:h=1.25 or FR5 thickness of 1.6mm

50 Ohms means a ratio of sqrt(L/C) so 0.12pF/mm is reading a bit high with 0.3nH/mm, not much, especially C3=1pF which has 10mm traces on either side to ground shunting C2,C4 and some coupling on C3.

You can shrink the length a bit and use proper thermal SMD pads. or shrink the C values. 5~10% If you want good return loss and have recalculated your values and confirmed Dk tolerance with supplier, depending on what return loss specs you expect. -15, -20 ,-30 you will need 2 or 1% parts.

  • \$\begingroup\$ Thank you for the advice. The values were chosen so that they match standard values, as it is extremely difficult for me to find supply of custom capacitance calacitors. I must use FR4 with 1.6mm thickness PCB, since that is the material my supplier works with. By the way, what do you mean by saying that adding coplanar grounds increases height? \$\endgroup\$ Jun 25, 2019 at 0:11
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    \$\begingroup\$ It lowers impedance or w:h ratio so for same 2mm w, h increases to std height of 1.6 \$\endgroup\$ Jun 25, 2019 at 0:12
  • \$\begingroup\$ Then the calculations are correct, aren't they? \$\endgroup\$ Jun 25, 2019 at 0:14
  • \$\begingroup\$ I would widen the coplanar gap to C3 or use 0.9pF =C3 or both but you have added some more spurious lobes with the layout but depends on your RL specs and phase specs \$\endgroup\$ Jun 25, 2019 at 0:15
  • \$\begingroup\$ Ok, I think I understood your point. I must take into account the parasitic capacitance of the transmission line if I want the filter to match the specs. Thank you very much for pointing that out, as I was not having it into account. \$\endgroup\$ Jun 25, 2019 at 0:18

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