Implementation of a coplanar waveguide in the design of a Butterworth filter

Question

I am trying to build a Butterworth bandpass from 130MHz to 140MHz (approx.). As I have already worked with microstrip lines of transmision, I wanted to give coplanar waveguides a try, as in the future I plan to work with higher frequencies (>10GHz) and I have been told that in those cases they behave more efficiently.

My coplanar waveguide is a feed line of 2mm spaced 0.49mm to ground. The board will be 1.6mm thick and use FR4 dielectric (relative permitivity of around 4.6). The expected impedance is 50 ohms.

As of now, I have finished designing my PCB, but I have two main doubts:

1. Can those soft curves on the upper ground plane, that KiCad adds automatically around the pads of the capacitors, affect the behavior of the waveguide?

2. Have I added too many vias around the signal line? And are there enough vias all over the rest of the board? I am a bit lost about vias.

Thank you in advance!

Edit 1: Thank you for the comments and answer, I have edited my design to this new PCB:

Edit 2: Thank you again for the information. This is the latest design. As I read here, it is necessary to add lots of small vias nexT to the main trace very close together. However, there is very little information about this on the internet, I cannot find any exact number/density of vias, their size or how far from the trace should thEy be.

Answer 1

Can those soft curves on the upper ground plane that KiCad adds automatically around the pads of the capacitors affect the behavior of the waveguide?

Above 10 GHz, they might.

In Altium I can add a "keep out" to prevent these features from being produced. You should be able to do something similar in KiCad.

Have I added too many viases around the signal line? And are there enought viases all over the rest of the board? I am a bit lost about viases

You can't really have too many vias. If you are not trying to save fractions of pennies, I wouldn't worry about too many vias.

The issue I would worry about (for a 10 GHz design, not for 100 MHz) is that where you tee your line to connect to the shunting LC components, you break the coplanar geometry. Without more analysis I couldn't say what frequency that will start to affect your performance, but at some point it will.

Thank you for the comments and answer, I have edited my design to this new PCB:

Ideally, don't make stubs to connect the L and C. Just put their pads right on the main signal trace. Allow the ground to fill in under the part so you maintain your 0.49 mm from the trace to ground.

Spread out C1, C3, and C5 if you have to to make things fit.

Doesn't particularly matter if you have L on one side of the trace and C on the other (assuming you can fit two pads on the trace without changing the trace width), or both on the same side of the trace.

Answer 2

With FR4 50 Ohms tracks just under 2:1 track width:height above ground plane so 2mm track means about 1m dielectric thickness if DK=4.4

Adding Coplanar grounds with 0.49 mm gap increases height so w:h=1.25 or FR5 thickness of 1.6mm

50 Ohms means a ratio of sqrt(L/C) so 0.12pF/mm is reading a bit high with 0.3nH/mm, not much, especially C3=1pF which has 10mm traces on either side to ground shunting C2,C4 and some coupling on C3.

You can shrink the length a bit and use proper thermal SMD pads. or shrink the C values. 5~10% If you want good return loss and have recalculated your values and confirmed Dk tolerance with supplier, depending on what return loss specs you expect. -15, -20 ,-30 you will need 2 or 1% parts.