1   |0|0|1
2   |1|0|1
3   |1|1|0
4   |1|0|0

From the truth table above, I can not find the equivalent boolean expression hence I can not create the logic circuit. Does it have any?

  • 4
    \$\begingroup\$ Is this a truth table or a transition table? \$\endgroup\$ – The Photon Jun 24 '19 at 23:21
  • \$\begingroup\$ My question came from a job interview. After I thought about it, this is more likely a transition table. Thanks for the hint. If it is a transition table, can it be translated to a digital circuit? What subject should I learn to solve this problem? \$\endgroup\$ – Ηλεκτρολόγος Μηχανικός Jun 24 '19 at 23:40
  • \$\begingroup\$ The table was used to drive a DC motor. \$\endgroup\$ – Ηλεκτρολόγος Μηχανικός Jun 24 '19 at 23:41
  • \$\begingroup\$ A and B are the outputs of some sensor. \$\endgroup\$ – Ηλεκτρολόγος Μηχανικός Jun 24 '19 at 23:43
  • 1
    \$\begingroup\$ My guess is that the interviewer really wanted to see what kind of questions you would ask about the table. If it is a transition table, then in general you need to learn how to design Finite State Machines. \$\endgroup\$ – Elliot Alderson Jun 25 '19 at 11:24

Your table is not a truth table, but a sequence table.

So you could choose to add two bits to represent the step (say S1/S0), make a counter or a grey code sequence for it using flip-flops, and then determine A, B and C based on the values of S1 and S0.

You have the free choice over S1 and S0, but not over the sequence for ABC.

It is not clearly specified what happens when you reach step 4 - is the sequence repeated or not?

Method 1

Lacking further specification, I would set S0 and S1 to an initial state on reset, and let them stuck in the final 4th state at the end.

To optimise, I check if any of the outputs A, B and/or C can substitute for S0 and/or S1.
I note that C takes two times the value 1, and two times 0. So C could be S1. Neither A or B could substitute for S0 because they do not have this same property.

I would choose S0 to be A xor B as it is likely an interesting choice.

So :

Step S0 S1 A B C
1 0 1 0 0 1
2 1 1 1 0 1
3 0 0 1 1 0
4 1 0 1 0 0

The clock should have S1 and S0 change to the values in the next step.

Logic (excluding S1,S0):

  • A=S0+not(S1)
  • B=not(S0+S1)
  • C=S1

Method 2

The other solution would be to use A,B and C only and determine the next A, B and C values based on the previous A, B and C values.

Then I would build:

Step A B C nextA nextB nextC
1 0 0 1 1 0 1
2 1 0 1 1 1 0
3 1 1 0 1 0 0
4 1 0 0 0 0 1


  • nextA=B+C
  • nextB=A&not(B)&C
  • nextC=not(A xor B)

There are a few formal techniques to reduce sequence tables. It's been a while since I learned them and applied them. Said otherwise, I can't explain them without going to look for them in my old notes.

I suppose that the examples are good enough.


I'm not entirely clear on the question you are asking. But I think the following satisfies the requirements:


simulate this circuit – Schematic created using CircuitLab

It's just an RS FF (two NOR gates) preceded by an AND and a NOR gate. See if that works for you.


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