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Most examples I find are for buck converters on a PCB of their own with massive traces. I want to make sure this layout is fine with the planes I'm using(both top and bottom copper pour layers are GND). I'm using a low output buck converter on a uC board I'm developing. The board will have USB to UART interface, uC, and 900 MHz radio. Total current draw is expected to be 70-100mAh, supply voltage to the board will be 12-30V. I'll leave out all these parts and just focus on the buck and buck components:

Buck: LT3970EMS-5#PBF (350mAh output max, 600Khz frequency). Inductor: ASPIAIG-S4035. R14 is just choosing frequency. Cap values are on layout. 1uF, 2.2uF, 47uF are Cin. 22uF is Cout.

All are ceramic except the 47uF. It's aluminum obviously. I have this because of what the datasheet says about capacitor transients when this device is powered from a power supply.

The data sheet has a PCB layout guideline that I found confusing. I left the Vin and Vout traces stubbed off as this hasn't been integrated into the circuit yet. I've included a close up on the pins so you guys can see the pin names. Thanks!

Top layer.

Bottom

Pins

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  • \$\begingroup\$ Ok, so what is the specific problem that you see? At a glance it looks like you followed typical layout topology for a SMPS IC. Are you concerned about noise at Vout? Linear Technology has great datasheets with lots of useful data plus examples. What are you missing? \$\endgroup\$
    – user105652
    Jun 25, 2019 at 2:17
  • \$\begingroup\$ The radio will need better ripple rejection like an LDO as RF Amps have poor PSRR. \$\endgroup\$ Jun 25, 2019 at 4:44
  • \$\begingroup\$ A schematic example would be nice \$\endgroup\$
    – Voltage Spike
    Jun 25, 2019 at 6:13
  • \$\begingroup\$ It looks pretty good. I would swap the locations of the 1uF and 2.2uF input caps (you want the smaller geometry caps with higher self resonance frequency closer to the controller). I would also rotate the 47uF cap 90 degrees to keep its ground connection closer to the IC. \$\endgroup\$
    – joribama
    Jun 25, 2019 at 6:19
  • \$\begingroup\$ @Sparky256 I was concerned about the feedback trace running under the controllers pins on the bottom layer of the board shown in blue. I'm concerned about EMI. I've read somewhere that certain grounds should stay isolated , then grouped to main ground at a single point, any advice? Also concerned with ripple on Vout. The data sheet on the radio says no more than 50 mV peak to peak. Of course I want to be well under 50. If there's too much ripple, I can just add more capacitors close to Vout without any changes in EMI correct? \$\endgroup\$
    – James Pie
    Jun 25, 2019 at 12:43

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