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When I change .vhd files I need to regenerate Qsys and then compile the design. How can I use tcl commands inside Quartus to regenerate the Qsys and then compile the project as well?​

Is there a way to automatically generate the Qsys systems when project is compiled? Why is this not done automatically? The problem arises since Qsys keeps local copies of the HDL source files.

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    \$\begingroup\$ It shouldn't be necessary to rerun Qsys every time you compile. What exactly are you doing? \$\endgroup\$ – Dave Tweed Jun 25 '19 at 14:52
  • \$\begingroup\$ There are some custom components. Git is being used to source control the vhd files. These source files change when we move to different branch but the local copies of Qsys do not. We require to rerun Qsys generate to update those local copies. \$\endgroup\$ – Quantum0xE7 Jun 26 '19 at 6:36
  • \$\begingroup\$ This seems odd. Where are you storing the QSys generated vhd files and are you ignoring them in Git? I currently have several projects containing QSys components and have never needed to regenerate when switching branches. \$\endgroup\$ – Vance Jun 26 '19 at 12:27
  • \$\begingroup\$ Basically, it is like this. I make change to custom component in Qsys i.e change its VHDL code. Now, I must regenerate the Qsys and then (after that) compile the project so the hardware shall incorporate the changes that I have made to the custom component. Anyway, is there no tcl command to generate the system? \$\endgroup\$ – Quantum0xE7 Jun 26 '19 at 12:30
  • \$\begingroup\$ I think I see now. Generally, it's sub-optimal to manually edit the QSys generated files for this very reason. While you can edit away, the new files won't be added to the QSys instantiation in your project until you run generate vhdl code. This is unlike standalone hdl files which will have the latest saved version grabbed during synthesis so I can see why it feels a little unintuitive. \$\endgroup\$ – Vance Jun 26 '19 at 12:43
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Does including this in your QSF solve your problem?

set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP
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  • \$\begingroup\$ Shall have to check this \$\endgroup\$ – Quantum0xE7 Mar 5 '20 at 12:24
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With help from $QUARTUS_ROOT/ip/altera:

set qsys_file <your_file>.qsys
set project_file <your_project>.qpf
qexec "qsys-generate --quartus-project=$project_file --synthesis=VHDL $qsys_file"
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  • \$\begingroup\$ I guess this is the only way there is ... \$\endgroup\$ – Quantum0xE7 Sep 20 '20 at 20:12
  • \$\begingroup\$ I think so. They should publish a TCL package like the flow package just for Qsys, but atm there is none. \$\endgroup\$ – Xerusial Sep 20 '20 at 21:53

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