I understand a Verilog code is made up of modules there are RTL codes where a lot of submodules can be instantiated in the main module. If I assume the main module(the top one) to be the parent and all the other submodules instantiated inside children. The child can be hard module or a soft module, I kind of know the difference but want a better explanation if possible
Soft cores are standard logic modules, written in Verilog or VHDL. They are called 'soft' because they are implemented in the re-programmable logic of the FPGA. You can edit and modify a soft module to tailor it to your needs. If you decide to change the module later, you can just re-program it, and the gates will be re-arranged according to your changes.
On the other hand, hard cores are not user-editable. Sometimes, this is because the hard core is implemented with fixed hardware on the chip, rather than re-programmable logic.
A good example of these concepts is the Xilinx Zynq family of chips, which incorporate both hard and soft cores. Some of the space on the Zynq chip is provided as a permanent ARM-core processor, similar to what you'd find on any CPU chip. This region is the Programmable System (PS) and can be thought of as a 'hard' module, because that area cannot be re-used as some other module type. It's defined in hardware to be an ARM core. You can turn certain features on and off, but the logic module must reflect that the hardware is fixed.
However, the rest of the Zynq's chip area is re-programmable FPGA logic. You can define whatever modules you want to implement your design in the Programmable Logic (PL) region. Any modules implemented in the PL would be 'soft' modules, because they are reconfigurable.