I have 12 SPI slaves, supporting SPI at a maximum clock rate of 2MHz. The SPI master (an ESP32), can run at up to 80MHz (and integer divisions thereof). My slaves are all 8-channel ADCs (MCP3208), which I need to poll continously. Therefore, I want to somehow maximize the throughput.
I was thinking that it might be possible to do time-division multiplexing on the slaves, by running the master at 40 MHz and create 20 time divisions, each being a 2MHz line for a potential slave. This would effectively combine my slaves into a single SPI device with higher speed (while interleaving all bits for the master). Unfortunately, I cannot find any resources on this topic.
Below is a diagram showing the concept, by using an external clock divider to create a 2MHz clock from the 40MHz base clock (which should ideally be offset for each slave..), a multiplexer for MOSI, and a demultiplexer for MISO lines.
Unfortunately, I am missing the required background knowledge to judge if this is at all possible, and if the required ICs even exist.