# Generate clock jitter in a testbench

How would you generate clock jitter in a testbench?

I have seen these two ways, but I am not sure if they are the best ways:

always #(period/2+$random(-jitter/2,jitter/2) ) clk = ~clk; always #(period/2+$dist_uniform(seed,-jitter,jitter)) clk = ~clk;

• It really depends on what your testbench is trying to test by introducing jitter. Are there multiple clocks that need to keep in phase, then you need to make sure the overall frequency remains the same and just move the edges. Commented Jun 27, 2019 at 1:41
• Define "best". Also, define what it is you hope to learn by simulating jitter. I've never seen the point -- If you think you have potential setup/hold violations, static timing analysis is a much more useful tool. If you're trying to determine the jitter transfer characteristics of a system, there are more direct ways to analyze that, too. Otherwise, you have to run a very long simulation in order to gather a statistically significant amount of data. Commented Jun 27, 2019 at 12:22

random generates pseudo-random numbers between -jitter/2 and jitter/2 but as far as I know there is no constraint on the distribution of the numbers. So the "randomness" of the numbers might be crappy, i.e. there might be an obvious pattern for the random numbers generated.

dist_uniform as the name implies generate random numbers uniformly (uniform distribution) between -jitter and jitter.

What kind of jitter are you expecting? Gaussian jitter? In that case you should use a normal distribution.

Secondly, why do you need to simulate jitter? You want to test potential race conditions due to sampling?

I'm not sure that a Verilog simulation is the best tool for that problem...

• jitter means shake in rising or falling edge of a clock signal at about a few nano seconds or micro seconds and its not always constant. Commented Sep 20, 2022 at 18:06
• @AmitM I know that
– Ben
Commented Sep 21, 2022 at 2:18