It's supposed to be a 32 bit DDR bus (well, 36 bit as it is 32 data plus 4 control). So the clock is 156.25 MHz (10G/64), and both edges are used, so that gives you 312.5 MT/s. See IEEE 802.3 22.214.171.124:
TXD<31:0> shall transition synchronously with respect to both the rising and falling edges of TX_CLK. For each high or low TX_CLK transition, data and/or control are presented on TXD<31:0> to the PHY for transmission
That's obviously a reference to a DDR interface. Same thing applies to TXC. Also, take a look at the timing diagrams in figures 46-5 and 46-6 on page 451 of IEEE 802.3-2018. These show that the data is definitely running at 2x the clock frequency.
Now, when you're on chip you don't necessarily implement it as a DDR interface. You'll likely either do 32 bit SDR at 312.5 MHz or 64 bit SDR at 156.25 MHz. For off chip stuff, these days nobody uses XGMII, it's either XAUI (4x3.125 Gbps) or XFI (1x10.3125 Gbps). So you never really see DDR XGMII.
In contrast, the XLGMII/CGMII interfaces are intended only for use on-chip, and are defined differently as SDR interfaces, see 802.3 126.96.36.199:
The values of TXC<7:0> and TXD<63:0> shall be sampled by the PHY on the rising edge of TX_CLK. TX_CLK is sourced by the RS.
The TX_CLK frequency shall be one-sixty-fourth of the MAC transmit data rate.
In practice, XLGMII/CGMII are usually unrolled even further. I think a 320 bit interface is relatively common (5 64 bit words per clock cycle).