I'm currently reading the IEEE XGMII specification (IEEE Std 802.3-2005 Clause 46) and I'm really surprised because it mentions a 32b data width for a frequency of 156.25MHz.

The 156.25MHz frequency is for a 64b data width, not 32b.

I read this error almost everywhere.

Why? Can't we even trust the specs?!

  • \$\begingroup\$ I'm not a big computer guy, but, it looks like 32 bits is the width for both the transmit and receive packages? In order to do 10 Gb/s wouldn't you need to send AND receive? So 64 bits round trip? \$\endgroup\$ – C. Lange Jun 27 '19 at 4:06
  • \$\begingroup\$ No, 10G is per RX/TX lane. My comment is correct. Somehow the spec is wrong. \$\endgroup\$ – Alexis Jun 27 '19 at 4:13
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    \$\begingroup\$ Spec is correct, you just read it wrong \$\endgroup\$ – alex.forencich Jun 27 '19 at 9:32

It's supposed to be a 32 bit DDR bus (well, 36 bit as it is 32 data plus 4 control). So the clock is 156.25 MHz (10G/64), and both edges are used, so that gives you 312.5 MT/s. See IEEE 802.3

TXD<31:0> shall transition synchronously with respect to both the rising and falling edges of TX_CLK. For each high or low TX_CLK transition, data and/or control are presented on TXD<31:0> to the PHY for transmission

That's obviously a reference to a DDR interface. Same thing applies to TXC. Also, take a look at the timing diagrams in figures 46-5 and 46-6 on page 451 of IEEE 802.3-2018. These show that the data is definitely running at 2x the clock frequency.

Now, when you're on chip you don't necessarily implement it as a DDR interface. You'll likely either do 32 bit SDR at 312.5 MHz or 64 bit SDR at 156.25 MHz. For off chip stuff, these days nobody uses XGMII, it's either XAUI (4x3.125 Gbps) or XFI (1x10.3125 Gbps). So you never really see DDR XGMII.

In contrast, the XLGMII/CGMII interfaces are intended only for use on-chip, and are defined differently as SDR interfaces, see 802.3

The values of TXC<7:0> and TXD<63:0> shall be sampled by the PHY on the rising edge of TX_CLK. TX_CLK is sourced by the RS.

The TX_CLK frequency shall be one-sixty-fourth of the MAC transmit data rate.

In practice, XLGMII/CGMII are usually unrolled even further. I think a 320 bit interface is relatively common (5 64 bit words per clock cycle).

  • \$\begingroup\$ DDR bus at 10G using XGMII? \$\endgroup\$ – Alexis Jun 27 '19 at 9:23
  • \$\begingroup\$ Yep. Was meant to be the next version of GMII, which is 8 bit SDR. But 64 bits is a lot of wires, so they went with 32 bit DDR. \$\endgroup\$ – alex.forencich Jun 27 '19 at 9:25
  • \$\begingroup\$ Before downvoting me, you should read the spec.... \$\endgroup\$ – alex.forencich Jun 27 '19 at 9:43
  • \$\begingroup\$ You mean 32b DDR bus at 156.25MHz. That means 32b bus SDR at 312.5MHz, that means 64b bus SDR at 156.25MHz. \$\endgroup\$ – Alexis Jun 27 '19 at 9:55
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    \$\begingroup\$ Also, it's certainly possible to design a 64b/66b encoder that processes 32 bits per clock cycle. Might give you an area or latency improvement for some applications. \$\endgroup\$ – alex.forencich Jun 27 '19 at 10:16

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