I am considering using Schottky diode to lower PMOS's Vth as the following diagram: enter image description here

As the current extracted from Schottky diode is small enough to provide 0.3-0.4V voltage drop, PMOS's threshold voltage will decrease due to body effect. Thus, PMOS only requires small vgs to be turned on.

However, some people say this method is impractical or rare to see in low voltage IC design. I would like to know if there is any drawback when we use it in LDO. Thanks!

  • \$\begingroup\$ XY problem. Why do you need lower Vgsth in the first place? \$\endgroup\$ – winny Jun 27 '19 at 6:27
  • \$\begingroup\$ To lower the source voltage of PMOS \$\endgroup\$ – dinex Jun 27 '19 at 8:18
  • \$\begingroup\$ To lower the source voltage of PMOS Why is that needed? You basically have a PMOS diode which cannot drop less voltage than Vt. There is no way around that. If you want to drop a smaller voltage you must use a different component (like a diode or a resistor) or make a circuit to do the function. \$\endgroup\$ – Bimpelrekkie Jun 27 '19 at 8:28
  • \$\begingroup\$ That’s not a goal in itself! Explain why you need it \$\endgroup\$ – winny Jun 27 '19 at 8:36
  • \$\begingroup\$ Sorry for posting wrong figure. Actually I am designing the buffer stage of LDO. I just want to lower vgs so the output level can be low enough to drive pass transistor. \$\endgroup\$ – dinex Jun 27 '19 at 9:13

This cannot work. It is not possible to lower the threshold voltage. The threshold voltage can only be increased by having a voltage between backgate (bulk) and source. See the relevant article on Wikipedia.

If there was some way to lower the threshold voltage of a MOSFET through a "circuit trick" then for sure I would know and use that trick. I've been dealing with CMOS circuits for more than 25 years.

The only way to lower the threshold voltage is to change the physical properties of the MOSFET (doping, oxide thickness etc.).

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  • \$\begingroup\$ I bet the integrated LDO ICs achieve their low dropout by having specially doped/designed integrated PMOS pass elements for the integrated op-amp to control. I expect their internal PMOST FET's Vgs must be at least, or slightly less than, the specified drop-out voltage, in order to operate and keep regulation. \$\endgroup\$ – KyranF Jun 27 '19 at 8:15
  • \$\begingroup\$ @KyranF No that is not the case. "specially doped" means: extra process step, extra mask(s) which equals more expensive. Also, it is simply not needed. For an LDO a "normal Vt" transistor can be used. A low Vt device would make sense for a regulator with a common drain output stage but that will never achieve the same low drop voltage as an LDO. I suggest that you study LDO designs to learn how that works, start here: analog.com/en/design-center/landing-pages/001/… \$\endgroup\$ – Bimpelrekkie Jun 27 '19 at 8:22
  • \$\begingroup\$ Thanks for the info and link! :) \$\endgroup\$ – KyranF Jun 27 '19 at 8:26
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    \$\begingroup\$ @dinex I cannot make heads or tails from that article. In my opinion: the author has no clue what he's writing about. Most of his article is "general observations" (example: the use of integrated circuits (ICs) has exploded over the past decade.) Didn't you notice that this has already been going on for the last 40 years?! There's no schematic in the article at all. I really think it would be wise to ignore this article. There might be a point in switching the connection of the backgate in certain situations but that isn't explained in this article. \$\endgroup\$ – Bimpelrekkie Jun 27 '19 at 8:52
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    \$\begingroup\$ It is possible to lower a PMOS threshold voltage using body bias. I have done it using commercial CMOS processes. The fact that the references are old papers, or you don't think it will "help much", or you think some article is poorly written does not change that fact. The second sentence in your answer is incorrect. \$\endgroup\$ – Elliot Alderson Jun 27 '19 at 11:18

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